You copied the Doc URL to your clipboard.

4.3. Mixed-endian access support

In the processor, instruction endianness and data endianness are separated:


Instructions are fixed little-endian.


Data accesses can be either little-endian or big-endian as controlled by the E bit in the Program Status Register.

On any exception entry, including reset, the EE bit in the CP15 c1 Control Register determines the state of the E bit in the CPSR. See c1, Control Register for details.

See the ARM Architecture Reference Manual for more information on mixed-endian access support.