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Appendix C. Revisions

This appendix describes the technical changes between released issues of this book.

Table C.1. Differences between issue F and issue G
Added description of product documentation and architectureProduct documentation and architecture
Updated reset value of Main ID Register
Updated bit assignments and description of Auxiliary Control Registerc1, Auxiliary Control Register
Show effect of improved cache maintenanceTable 3.73
Changed description of values for predefined events 0x45 and 0x46Table 3.97
Expanded description of DT field in PLE Control RegisterTable 3.126
Updated description of L1 memory system
Added section on instruction cache maintenanceInstruction cache maintenance
Reorganized tables for AXI ID assignmentsAXI identifiers
Updated descriptions of AXI address channel for data transactionsTable 9.7
Added table showing number of transfers on AXI write channel for an evictionEvictions
Clarified timing diagram of STANDBYWFI deassertionFigure 10.8
Updated field values for Debug ID RegisterCP14 c0, Debug ID Register
Updated field values for Peripheral ID Register 2
Updated ID Register bit assignmentsFigure 14.2
Added tables to show the effect of CP15 cache maintenanceCoprocessor instructions
Added footnote to clarify back-to-back execution of certain multiply and multiply-accumulate instructionsTable 16.19
Added Note to clarify operation of Advanced SIMD floating-point instructionsAdvanced SIMD floating-point instructions
Expanded description of VFP instruction executionVFP instruction execution in the NFP pipeline

Table C.2. Differences between issue G and issue H
Amended function description for invalidate instruction cache lineTable 3.73

Table C.3. Differences between issue H and issue I
Updated Product revisions informationProduct revisionsAll revisions
Updated Main ID Register to reflect revision changer3p0
Modified description for bits [7:4] and [3:0] in the Debug ID RegisterTable 12.11All revisions
Modified description for the Revision field in the Peripheral Identification RegistersTable 12.45All revisions
Updated description and reset value for bits [7:4] in the Peripheral ID Register 3r3p0
Updated value for bits [3:0] of the FPSID RegisterTable 13.7r3p0
Changed the name for trigger input 0 from DBGTRIGGER to Debug entry.r3p0
Added text to clarify description for trigger input 0Table 15.1All revisions
Added a note to clarify description for trigger outputs 0 and 8Trigger inputs and outputsAll revisions
Updated the value and description for bits [4:0] of the CTI Device ID RegisterAll revisions
Added text to clarify description for bit [0] of the CTI Interrupt Acknowledge RegisterTable 15.5All revisions
Updated description for the load data miss replay eventTable 16.16All revisions
Clarified description of dual issue for Advanced SIMD instructionsDual issue for Advanced SIMD instructionsAll revisions

Table C.4. Differences between Issue I and Issue J
Updated Product revisions informationProduct revisionsAll revisions
Updated Main ID Register to reflect revision changer3p2

Corrected reset values for the following registers:

  • Cache Type

  • Processor Feature 0

  • Memory Model Feature 0

  • Memory Model Feature 3

  • Instruction Set Attribute 1

Table 3.3 
Updated description and reset value for bits [7:4] in the Peripheral ID Register 3r3p2
Modified description for bits [7:4] of Memory Model Feature Register 0 Table 3.19All revisions
Provided instruction to write the Cache Size Selection Registerc0, Cache Size Selection RegisterAll revisions
Added footnote to clarify reset values for Secure and Non-secure banked access for the Control RegisterTable 3.46All revisions
Modified table to correctly indicate when the value of the L2EN bit has no effect on processor behavior when enabling cachesTable 3.48All revisions
Specified the reset value of the L2EN field of the Auxiliary Control RegisterTable 3.49All revisions
Expanded Note to include description of Monitor mode access to non-secure banked copies of registersc1, Secure Configuration RegisterAll revisions
Modified descriptions of events 0x45 and 0x46Table 3.97All revisions
Added description for cache flow when both L1 and L2 are cacheable, write-back, write-allocateTable 7.1All revisions

Table C.5. Differences between Issue J and Issue K
Updated description for CRm=c6 Opcode_2=1 cache and prefetch buffer maintenance operationTable 3.73All revisions
Revised description of how the Cortex-A8 uses the CLK signal.Clock domainsAll revisions
Updated description of the effect of a reset on the NEON and VFP clocks.NEON or ETM unit level gatingAll revisions
Added NOTE to describe Debug behavior in systems with no ROM Table.All revisions
Updated code for the code for transmit data transfer.Example 12.4All revisions
Updated the code for polling the DCC.Example 12.6All revisions
Updated the sequence for reading a block of words of memory.Example 12.25All revisions
Revised description of Floating-Point Status and Control Register.Floating-Point Status and Control Register, FPSCRAll revisions
Revised description of Floating-Point Exception Register.Floating-point Exception Register, FPEXCAll revisions

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