Similar to the multiple clock domains within the processor, there are multiple reset domains:
All resets are active-LOW inputs, and each reset can affect one or more clock domains. Table 10.1 shows the different resets and what areas of the processor are controlled by those resets.
|Signal||Core (CLK)||NEON (CLK)||ETM (CLK)||Debug (CLK)||APB (PCLK)||ATB (ATCLK)|
There are specific requirements that must be met to reset each clock domain within the processor. Not adhering to these requirements can lead to a clock domain that is not functional.
The documented reset sequences are the only reset sequences validated. Any deviation from the documented reset sequences might cause an improper reset of the clock domain.