During a power-on reset or soft reset, by default the processor clears the valid bits of both the L1 data cache and the L2 unified cache. Depending on the size of the L2 cache, this can take up to 1024 cycles after the deasserting edge of the reset signals. The L1 data cache reset can take up to 512 cycles, and occurs coincident with the L1 instruction cache reset. The processor does not begin execution until the L1 caches are reset. The L2 hardware reset occurs in the background and does not interfere with reset code. Any attempt to enable the L2 unified cache or perform any L2 cache maintenance operations stalls the processor until the hardware reset is complete.
The processor has two pins, L1RSTDISABLE and L2RSTDISABLE, to control the hardware reset process. The usage models of the hardware reset pins are as follows:
For applications that do not retain the L1 data cache and L2 unified cache RAM contents throughout a core power-down sequence, the hardware resets both the L1 data cache and L2 unified cache at every reset, using ARESETn or nPORESET. Both L1RSTDISABLE and L2RSTDISABLE must be tied LOW. This is the recommended usage model.
For applications that do retain the L1 data cache or L2 unified cache RAM contents throughout a core power-down sequence, hardware must control both the L1RSTDISABLE and L2RSTDISABLE signals during reset. When the system is powering up for the first time, the hardware reset signals, L1RSTDISABLE and L2RSTDISABLE, must be tied LOW to invalidate both the L1 data cache and L2 unified cache RAM contents using the hardware reset mechanism. If either the L1 data cache or L2 unified cache must retain its data during a reset sequence, then the corresponding hardware reset disable must be tied HIGH.
If the hardware array reset mechanism is not used, then both the L1RSTDISABLE and L2RSTDISABLE pins must be tied HIGH.
Both the L1RSTDISABLE and L2RSTDISABLE pins must be valid at least 16 CLK cycles before and after the deasserting edge of ARESETn and nPORESET.