The BTB does not have to be invalidated on a context switch, self-modifying code, or any other change in the VA-to-PA mapping.
ARMv7-A specifies two branch prediction invalidation operations:
MCR p15, 0, Rx, c7, c5, 6 ; invalidate entire branch predictor array
MCR p15, 0, Rx, c7, c5, 7 ; invalidate VA from branch predictor array
These operations are not required to perform a context switch in the processor and are implemented as NOPs. ARMv7-A generic context-switching or self-modifying code can contain these operations without cycle penalty. These instructions can be enabled by setting the IBE bit in the Auxiliary Control Register to 1. See c1, Auxiliary Control Register for details.