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5.6.1. Instruction memory barriers

ARMv7-A requires Instruction Memory Barriers (IMBs) after updates to certain CP15 registers or CP15 operations. The processor flushes the pipeline to ensure that the instructions following the given CP15 instruction are fetched in the new context. In addition, self-modifying code sequences must be preceded by an IMB. The recommended means of implementing an IMB is the ISB instruction.

The following prefetch flush instruction is from earlier versions of the ARM architecture. The processor supports this instruction, but its use is deprecated in ARMv7-A.

MCR p15, 0, Rx, c7, c5, 4
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