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5.2. Predicted instructions

This section shows the instructions that the processor predicts. Unless otherwise specified, the list applies to ARM, Thumb-2, and ThumbEE instructions. See the ARM Architecture Reference Manual for more information about instructions or addressing modes.

The flow prediction hardware predicts the following instructions:

  • B conditional

  • B unconditional

  • BL

  • BLX(1) immediate

    The BL and BLX(1) instructions act as function calls and push the return address and ARM or Thumb state onto the return stack.

  • BLX(2) register

    The BLX(2) instruction acts as a function call and pushes the return address and ARM or Thumb state onto the return stack.

  • BX

    The BX r14 instruction acts as a function return and pops the return address and ARM or Thumb state from the return stack.

  • LDM(1) with PC in the register list in ARM state

    The LDM instruction with r13 specified as the base register acts as a function return and pops the return address and ARM or Thumb state from the return stack.

  • POP with PC in register list in Thumb state

    The POP instruction acts as a function return and pops the return address and ARM or Thumb state from the return stack.

  • LDM with PC in register list in Thumb or ThumbEE state

    The LDM instruction with r13 specified as the base register, or r9 specified as the base register in ThumbEE state acts as a function return and pops the return address and ARM or Thumb state from the return stack.

  • LDR with PC destination

    The LDR instruction with r13 specified as the base register, or r9 specified as the base register in ThumbEE state, acts as function return and pops the return address and ARM or Thumb state from the return stack.

  • PC-destination data-processing operations in ARM state

    In ARM state, the second operand of a data-processing instruction can be a 32-bit immediate value, an immediate shift value, or a register shift value. An instruction with an immediate shift value or a register shift value is predicted. An instruction with a 32-bit immediate value is not predicted. For example:

    • MOV pc, r10, LSL r3 is predicted

    • ADD pc, r0, r1, LSL #2 is predicted

    • ADD pc, r4, #4 is not predicted.

    There is no restriction on the opcode predicted, but a majority of opcodes do not make sense for branch-type instructions. Usually only MOV, ADD, and SUB are useful.

    Note

    Instructions with the S suffix are not predicted. They are typically used to return from exceptions and have side effects that can change privilege mode and security state.

  • ADD(4) with PC destination in Thumb state

  • MOV(3) with PC destination in Thumb state

  • CPY with PC destination in Thumb state

  • CZB in Thumb state

  • TBB/TBH in Thumb state

    Note

    In Thumb state, a branch that is normally encoded as unconditional can be conditioned by inclusion in an If-Then-Else (ITE) block. Then it is treated as a normal conditional branch.

  • HB (ThumbEE state only)

  • HBP (ThumbEE state only)

  • HBL (ThumbEE state only)

  • HBLP (ThumbEE state only).

    The HBL and HBLP instructions act as function calls and push the return address onto the return stack.

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