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3.5. Summary of CP15 instructions

Table 3.49 shows the CP15 instructions that you can use arranged numerically.

CP15 instruction summary
InstructionOperationReference

MRC p15, 0, <Rd>, c0, c0, 0

MRC p15, 0, <Rd>, c0, c0, 1

MRC p15, 0, <Rd>, c0, c0, 3

MRC p15, 0, <Rd>, c0, c0, 5

MRC p15, 0, <Rd>, c0, c0, 0

MRC p15, 0, <Rd>, c0, c1, 1

MRC p15, 0, <Rd>, c0, c1, 2

MRC p15, 0, <Rd>, c0, c1, 4

MRC p15, 0, <Rd>, c0, c1, 5

MRC p15, 0, <Rd>, c0, c1, 6

MRC p15, 0, <Rd>, c0, c1, 7

MRC p15, 0, <Rd>, c0, c2, 0

MRC p15, 0, <Rd>, c0, c2, 1

MRC p15, 0, <Rd>, c0, c2, 2

MRC p15, 0, <Rd>, c0, c2, 3

MRC p15, 0, <Rd>, c0, c2, 4

Read ID Code Register

Read Cache Type Register

Read TLB Type Register

Read CPU ID Register

Read Proc Feature Register 0

Read Proc Feature Register 1

Read Debug Feature Register 0

Read Memory Feature Register 0

Read Memory Feature Register 1

Read Memory Feature Register 2

Read Memory Feature Register 3

Read ISA Feature Register 0

Read ISA Feature Register 1

Read ISA Feature Register 2

Read ISA Feature Register 3

Read ISA Feature Register 4

c0, ID Code Register

c0, Cache Type Register

c0, TLB Type Register

c0, CPU ID Register

c0, Feature registers

c0, Feature registers

c0, Feature registers

c0, Feature registers

c0, Feature registers

c0, Feature registers

c0, Feature registers

c0, Instruction set attributes registers

c0, Instruction set attributes registers

c0, Instruction set attributes registers

c0, Instruction set attributes registers

c0, Instruction set attributes registers

MRC p15, 0, <Rd>, c1, c0, 0

MCR p15, 0, <Rd>, c1, c0, 0

MRC p15, 0, <Rd>, c1, c0, 1

MCR p15, 0, <Rd>, c1, c0, 1

MRC p15, 0, <Rd>, c1, c0, 2

MCR p15, 0, <Rd>, c1, c0, 2

Read Control Register

Write Control Register

Read Auxiliary Control Register

Write Auxiliary Control Register

Read Coprocessor Access Control Register

Write Coprocessor Access Control Register

c1, Control Register

c1, Control Register

c1, Auxiliary Control Register

c1, Auxiliary Control Register

c1, Coprocessor Access Control Register

c1, Coprocessor Access Control Register

MRC p15, 0, <Rd>, c2, c0, 0

MCR p15, 0, <Rd>, c2, c0, 0

MRC p15, 0, <Rd>, c2, c0, 1

MCR p15, 0, <Rd>, c2, c0, 1

MRC p15, 0, <Rd>, c2, c0, 2

MCR p15, 0, <Rd>, c2, c0, 2

Read Translation Table Base Register 0

Write Translation Table Base Register 0

Read Translation Table Base Register 1

Write Translation Table Base Register 1

Read Translation Table Base Control Register

Write Translation Table Base Control Register

c2, Translation Table Base Register 0

c2, Translation Table Base Register 0

c2, Translation Table Base Register 1

c2, Translation Table Base Register 1

c2, Translation Table Base Control Register

c2, Translation Table Base Control Register

MRC p15, 0, <Rd>, c3, c0, 0

MCR p15, 0, <Rd>, c3, c0, 0

Read Domain Access Control Register

Write Domain Access Control Register

c3, Domain Access Control Register

c3, Domain Access Control Register

MRC p15, 0, <Rd>, c5, c0, 0

MCR p15, 0, <Rd>, c5, c0, 0

MRC p15, 0, <Rd>, c5, c0, 1

MCR p15, 0, <Rd>, c5, c0, 1

Read Data Fault Status Register

Write Data Fault Status Register

Read Instruction Fault Status Register

Write Instruction Fault Status Register

c5, Data Fault Status Register

c5, Data Fault Status Register

c5, Instruction Fault Status Register

c5, Instruction Fault Status Register

MRC p15, 0, <Rd>, c6, c0, 0

MCR p15, 0, <Rd>, c6, c0, 0

MRC p15, 0, <Rd>, c6, c0, 1

MCR p15, 0, <Rd>, c6, c0, 1

Read Fault Address Register

Write Fault Address Register

Read Watchpoint Fault Address Register

Write Watchpoint Fault Address Register

c6, Fault Address Register

c6, Fault Address Register

c6, Watchpoint Fault Address Register

c6, Watchpoint Fault Address Register

MCR p15, 0, <Rd>, c7, c0, 4

MRC p15, 0, <Rd>, c7, c4, 0

MCR p15, 0, <Rd>, c7, c5, 0

MCR p15, 0, <Rd>, c7, c5, 1

MCR p15, 0, <Rd>, c7, c5, 2

MCR p15, 0, <Rd>, c7, c5, 4

MCR p15, 0, <Rd>, c7, c5, 6

MCR p15, 0, <Rd>, c7, c5, 7

MCR p15, 0, <Rd>, c7, c6, 0

MCR p15, 0, <Rd>, c7, c6, 1

MCR p15, 0, <Rd>, c7, c6, 2

MCR p15, 0, <Rd>, c7, c7, 0

MCR p15, 0, <Rn>, c7, c8, 0

MCR p15, 0, <Rn>, c7, c8, 1

MCR p15, 0, <Rn>, c7, c8, 2

MCR p15, 0, <Rn>, c7, c8, 3

MCR p15, 0, <Rd>, c7, c10, 0

MCR p15, 0, <Rd>, c7, c10, 1

MCR p15, 0, <Rd>, c7, c10, 2

MCR p15, 0, <Rd>, c7, c10, 4

MCR p15, 0, <Rd>, c7, c10, 5

MCR p15, 0, <Rd>, c7, c14, 0

MCR p15, 0, <Rd>, c7, c14, 1

MCR p15, 0, <Rd>, c7, c14, 2

Wait For Interrupt

PA Register

Invalidate Entire Instruction Cache Register

Invalidate Instruction Cache Line (using MVA) Register

Invalidate Instruction Cache Line (using Index) Register

Flush Prefetch Buffer Register

Flush Entire Branch Target Cache Register

Flush Branch Target Cache Entry Register

Invalidate Entire Data Cache Register

Invalidate Data Cache Line (using MVA) Register

Invalidate Data Cache Line (using Index) Register

Invalidate Both Caches Register

VA to PA with privileged read permission check Register

VA to PA with privileged write permission check Register

VA to PA with user read permission check Register

VA to PA with user write permission check Register

Clean Entire Data Cache Register

Clean Data Cache Line (using MVA) Register

Clean Data Cache Line (using Index) Register

Drain Synchronization Barrier Register

Data Memory Barrier Register

Clean and Invalidate Entire Data Cache Register

Clean and Invalidate Data Cache Line (using MVA) Register

Clean and Invalidate Data Cache Line (using Index) Register

Table 3.29

PA Register

Invalidate, Clean, and Clean and Invalidate, Entire Data Cache operations

Table 3.29

Table 3.29

Table 3.29

Table 3.29

Table 3.29

Table 3.29

Table 3.29

Table 3.29

Table 3.29

Table 3.29

VA to PA Translation Register

VA to PA Translation Register

VA to PA Translation Register

VA to PA Translation Register

VA to PA Translation Register

Invalidate, Clean, and Clean and Invalidate, Entire Data Cache operations

Table 3.29

Table 3.29

Table 3.29

Table 3.29

Table 3.29

Invalidate, Clean, and Clean and Invalidate, Entire Data Cache operations

VA to PA Translation Register

VA to PA Translation Register

MCR p15,0, <Rd>, c8, C5, 0

MCR p15,0, <Rd>, c8, C5, 1

MCR p15,0, <Rd>, c8, C5, 2

MCR p15,0, <Rd>, c8, C5, 3

MCR p15,0, <Rd>, c8, C6, 0

MCR p15,0, <Rd>, c8, C6, 1

MCR p15,0, <Rd>, c8, C6, 2

MCR p15,0, <Rd>, c8, C6, 3

MCR p15,0, <Rd>, c8, C7, 0

MCR p15,0, <Rd>, c8, C7, 1

MCR p15,0, <Rd>, c8, C7, 2

MCR p15,0, <Rd>, c8, C7, 3

Invalidate Instruction TLB Register

Invalidate Instruction TLB Single Entry Register

Invalidate Instruction TLB Entry on ASID match Register

Invalidate Instruction TLB Single Entry on MVA only Register

Invalidate Data TLB Register

Invalidate Data TLB Single Entry Register

Invalidate Data TLB Entry on ASID match Register

Invalidate Data TLB Single Entry on MVA only Register

Invalidate Unified TLB Register

Invalidate Unified TLB Single Entry Register

Invalidate Unified TLB Entry on ASID match Register

Invalidate Unified TLB Single Entry on MVA only Register

c8, TLB Operations Register

MRC p15, 0, <Rd>, c9, c0, 0

MCR p15, 0, <Rd>, c9, c0, 0

Read Data Cache Lockdown Register

Write Data Cache Lockdown Register

c9, Data Cache Lockdown Register

c9, Data Cache Lockdown Register

MRC p15, 0, <Rd>, c10, c0, 0

MCR p15, 0, <Rd>, c10, c0, 0

MRC p15, 0, <Rd>, c10, c2, 0

MCR p15, 0, <Rd>, c10, c2, 0

MRC p15, 0, <Rd>, c10, c2, 1

MCR p15, 0, <Rd>, c10, c2, 1

Read TLB Lockdown Register

Write TLB Lockdown Register

Read Primary Remap Register

Write Primary Remap Register

Read Normal Remap Register

Write Normal Remap Register

c10, Memory remap registers

MRC p15, 0, <Rd>, c13, c0, 0

MCR p15, 0, <Rd>, c13, c0, 0

MRC p15, 0, <Rd>, c13, c0, 1

MCR p15, 0, <Rd>, c13, c0, 1

MRC p15, 0, <Rd>, c13, c0, 2

MCR p15, 0, <Rd>, c13, c0, 2

MRC p15, 0, <Rd>, c13, c0, 3

MCR p15, 0, <Rd>, c13, c0, 3

MRC p15, 0, <Rd>, c13, c0, 4

MCR p15, 0, <Rd>, c13, c0, 4

Read Process ID Register

Write Process ID Register

Read Context ID Register

Write Context ID Register

Read Thread ID User and Privileged Read Write Register

Write Thread ID User and Privileged Read Write Register

Read Thread ID User Read only Register

Write Thread ID User Read only Register

Read Thread ID Privileged Read Write only Register

Write Thread ID Privileged Read Write only Register

c13, FCSE PID Register

c13, FCSE PID Register

c13, Context ID Register

c13, Context ID Register

MRC p15, 0, <Rd>, c15, c12, 0

MCR p15, 0, <Rd>, c15, c12, 0

MRC p15, 0, <Rd>, c15, c12, 1

MCR p15, 0, <Rd>, c15, c12, 1

MRC p15, 0, <Rd>, c15, c12, 2

MCR p15, 0, <Rd>, c15, c12, 2

MRC p15, 0, <Rd>, c15, c12, 3

MCR p15, 0, <Rd>, c15, c12, 3

Read Performance Monitor Control Register

Write Performance Monitor Control Register

Read Cycle Counter Register

Write Cycle Counter Register

Read Count Register 0

Write Count Register 0

Read Count Register 1

Write Count Register 1

c15, Performance Monitor Control Register (PMNC)

c15, Performance Monitor Control Register (PMNC)

c15, Cycle Counter Register (CCNT)

c15, Cycle Counter Register (CCNT)

c15, Count Register 0 (PMN0)

c15, Count Register 0 (PMN0)

c15, Count Register 1 (PMN1)

c15, Count Register 1 (PMN1)

MCR p15, 5, <Rd>, c15, c4, 2

MCR p15, 5, <Rd>, c15, c4, 4

MRC p15, 5, <Rd>, c15, c5, 2

MCR p15, 5, <Rd>, c15, c5, 2

MRC p15, 5, <Rd>, c15, c6, 2

MCR p15, 5, <Rd>, c15, c6, 2

MRC p15, 5, <Rd>, c15, c7, 2

MCR p15, 5, <Rd>, c15, c7, 2

Read Main TLB Entry Register

Write Main TLB Entry Register

Read Main TLB VA Register

Write Main TLB VA Register

Read Main TLB PA Register

Write Main TLB PA Register

Read Main TLB Attribute Register

Write Main TLB Attribute Register

c15, TLB Debug Control Register

MRC p15, 7, <Rd>, c15, c1, 0

MCR p15, 7, <Rd>, c15, c1, 0

Read TLB Debug Control Register

Write TLB Debug Control Register

c15, TLB Debug Control Register
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