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Appendix C. Revisions

This appendix describes the technical changes between released issues of this book.s

Table C.1. Issue A
First release-

Table C.2. Differences between issue A and issue B
Load/Store Unit and address generation clarifiedFigure 1.1.
Fast loop mode changed to small loop mode
“Branch prediction” changed to “dynamic branch prediction”.
“LI cache coherency” changed to “L1 data cache coherency”Cortex-A9 variants.
Processor Feature Register 0 reset value correctedTable 4-29 on page 4-46.

PMSWINC descriptions made consistent

  • Table 4-29 on page 4-46

  • Software Increment Register on page 4-100.

MIDR bits[3:0] updated from 0 to 1Table 4.1.
ID_MMFR3 [23:20] bit value corrected to 0x1Table 4-42 on page 4-50.
AFE bit description correctedTable 4-51 on page 4-62.
Auxiliary Control Register bit field corrections
  • Table 4-52 on page 4-66

  • Figure 4-36 on page 4-66.

S parameter values correctedSet/Way format on page 4-83.
Bit descriptions of bits[11], [10], and [8] made consistent with tableFigure 4-41 on page 4-87.
Description of event 0x68 corrected, “architecturally” removed.Table 4-80 on page 4-123.
TLB lockdown entries number corrected from 8 to 4c10, TLB Lockdown Register on page 4-134.
A,I, and F bit descriptions correctedc12, Interrupt Status Register on page 4-147.
Number of micro TLB entries changed from 8 to 32Micro TLB.
Repeated information about cache types removedMicro TLB.
IRGN bits description amended from TTBCR to TTBR0/TTRBR1Main TLB.
Note about invalidating the caches and BTAC before use addedAbout the L1 memory system.
Parity support scheme information section addedParity error support.
L2 master interfaces, M0 and M1 listed and describedAbout the Cortex-A9 L2 interface.
Cross reference to DBSCR external description added. Footnote extended to include reference to the DBSCR external viewTable 10.1.
DBGDSCR description corrected with the addition of internal and external view descriptions.CP14 c1, Debug Status and Control Register (DBGDSCR) on page 8-9.
MOE bits descriptions re-ordered and extendedTable 8-2 on page 8-10.
Additional cross-references added from Table 10-1
  • Debug State Cache Control Register (DBGDSCCR) on page 8-8

  • CP14 c1, Debug Status and Control Register (DBGDSCR) on page 8-9

  • Device Power-down and Reset Status Register (DBGPRSR) on page 8-27

  • Integration Mode Control Register (DBGITCTRL) on page 8-45

  • Claim Tag Clear Register (DBGCLAIMCLR) on page 8-47

  • Lock Access Register (DBGLAR) on page 8-48

  • Lock Status Register (DBGLSR) on page 8-49

  • Authentication Status Register (DBGAUTHSTATUS) on page 8-49

  • Device Type Register (DBGDEVTYPE) on page 8-50.

Table 10-1 footnotes correctedTable 10.1.
Byte address field entries corrected.Table 10.8.
Interrupts signals descriptions correctedTable A.3.
AXI USER descriptions extended

Table C.3. Differences between issue B and issue C
2.8.1 LE and BE-8 accesses on a 64-bit wide bus removed.-
Chapter 4 Unaligned and Mixed-Endian Data Access Support removed.-
The power management signal BISTSCLAMP is removed.-
Dynamic high level clock gating added.Dynamic high level clock gating on page 2-9
TLB information updated.Table 1-1 on page 1-10, Table 4-10 on page 4-15, Table 4-37 on page 4-44
ID_MMF3[15:12] description shortened.Memory Model Features Register 3 on page 4-49
ACTLR updated to include reference to PL310 optimizations.Auxiliary Control Register on page 4-64
Addition of a second replacement strategy. Selection done by SCTLR.RR bit.System Control Register
Event information extended.Cortex-A9 specific events on page 4-32
DEFLAGS[6:0] added.DEFLAGS[6:0] on page 4-37, Performance monitoring signals
Power Control Register description added.Power Control Register on page 4-63
PL310 optimizations added to L2 memory interface descriptionOptimized accesses to the L2 memory interface
Addition of watchpoint address maskingWatchpoint Control Registers
Added debug request restart diagram.Effects of resets on debug registers
CPUCLKOFF information added.Table A.4,Unregistered signals on page B-3
DECLKOFF information added.Table A.4,Unregistered signals on page B-3
MAXCLKLATENCY[2:0] information added.Configuration signals
PMUEVENT bus description extended.Performance monitoring signals
PMUSECURE and PMUPRIV added.Performance monitoring signals
Description of serializing behavior of DMB updated.Serializing instructions

Table C.4. Differences between issue C and issue D
Preface updatedPreface
ARM Architecture Reference Manual moved to the top of Further ReadingARM publications
Block diagram includes Preload Engine (PE)Figure 1.1
Interrupt signals amended
Clarification of Data Engine optionsData Engine
Clarification of system design componentsSystem design components
Compliance clarificationsCompliance
PE added to featuresFeatures
Configurable options includes PE and PE FIFO sizeConfigurable options for the Cortex-A9 processor
NEON SIMD and FPU options clarifiedTable 1.1
Test Features section addedTest features
Power control description includes NEON SIMD clock gatingPower Control Register


Reset modes
nWDRESET added
Changes to voltage domain boundariesFigure 2.4
Content of 4.1 that duplicates ARM Architecture Reference Manual material removed 
Sentence about tying unused bits of PARITYFAIL HIGH removedParity error support
PE description addedChapter 8 Preload Engine
PMU description addedChapter 9 Performance Monitoring Unit
Debug updatedChapter 10 DebugChapter 10 Debug
Signals descriptions amended and extendedAppendix A Signal Descriptions
AC Characteristics Appendix removed 

Table C.5. Differences between issue D and issue E
No technical changes-

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