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A.4. Configuration signals

Table A.4 shows the configuration signals only sampled during reset of the processor.

Table A.4. Configuration signals
NameI/OSourceDescription
CFGENDISystem configuration control

Controls the state of EE bit in the SCTLR at reset:

0 = EE bit is LOW

1 = EE bit is HIGH

CFGNMFII

Configures fast interrupts to be nonmaskable:

0 = Clear the NMFI bit in the CP15 c1 Control Register

1 = Set the NMFI bit in the CP15 c1 Control Register.

TEINITI

Default exception handling state:

0 = ARM

1 = Thumb.

It sets the SCTLR.TE bit at reset.

VINITHII

Controls the location of the exception vectors at reset:

0 = Start exception vectors at address 0x00000000

1 = Start exception vectors at address 0xFFFF0000.

It sets the SCTLR.V bit.


Table A.5 shows the CP15SDISABLE signal.

Table A.5. CP15SDISABLE signal
NameI/OSourceDescription
CP15SDISABLEISecurity controller

Disables write access to some system control processor registers in Secure state:

0 = Not enabled

1 = Enabled.

See System Control Register.