Table A.4 shows the configuration signals only sampled during reset of the processor.
|CFGEND||I||System configuration control|
Controls the state of EE bit in the SCTLR at reset:
0 = EE bit is LOW
1 = EE bit is HIGH
Configures fast interrupts to be nonmaskable:
0 = Clear the NMFI bit in the CP15 c1 Control Register
1 = Set the NMFI bit in the CP15 c1 Control Register.
Default exception handling state:
0 = ARM
1 = Thumb.
It sets the SCTLR.TE bit at reset.
Controls the location of the exception vectors at reset:
0 = Start exception vectors at address
= Start exception vectors at address
It sets the SCTLR.V bit.
Table A.5 shows the CP15SDISABLE signal.
Disables write access to some system control processor registers in Secure state:
0 = Not enabled
1 = Enabled.