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Appendix C. Revisions

This appendix describes the technical changes between released issues of this book.s

Table C.1. Issue A
ChangeLocation
First release-

Table C.2. Differences between issue A and issue B
ChangeLocation
Clarified Load/Store Unit and address generation Figure 1.1.
Changed fast loop mode to small loop mode
Changed branch prediction to dynamic branch prediction
Changed LI cache coherency to L1 data cache coherencyCortex-A9 variants.
Corrected Processor Feature Register 0 reset value Table 4-29 on page 4-46.

Made PMSWINC descriptions consistent

  • Table 4-29 on page 4-46

  • Software Increment Register on page 4-100.

Updated MIDR bits[3:0] from 0 to 1Table 4-1 on page 4-5.
Corrected ID_MMFR3 [23:20] bit value to 0x1Table 4-42 on page 4-50.
Corrected AFE bit description Table 4-51 on page 4-62.
Corrected Auxiliary Control Register bit field
  • Table 4-52 on page 4-66

  • Figure 4-36 on page 4-66.

Corrected S parameter values Set/Way format on page 4-83.
Made descriptions of bits[11], [10], and [8] consistent with tableFigure 4-41 on page 4-87.
Corrected description of event 0x68 , architecturally removed.Table 4-80 on page 4-123.
Corrected TLB lockdown entries number from 8 to 4c10, TLB Lockdown Register on page 4-134.
Corrected A, I, and F bit descriptions c12, Interrupt Status Register on page 4-147.
Changed number of micro TLB entries from 8 to 32Micro TLB.
Removed repeated information about cache types Micro TLB.
Amended IRGN bits description from TTBCR to TTBR0/TTRBR1Main TLB.
Added note about invalidating the caches and BTAC before use About the L1 memory system.
Added parity support scheme information section Parity error support.
Listed and described L2 master interfaces, M0 and M1 About the Cortex-A9 L2 interface.
Added Cross reference to DBSCR external description . Extended Footnote to include reference to the DBSCR external viewTable 10.1.
Corrected DBGDSCR description with the addition of internal and external view descriptions.CP14 c1, Debug Status and Control Register (DBGDSCR) on page 8-9.
Re-ordered and extended MOE bits descriptions Table 8-2 on page 8-10.
Added more cross-references from Table 10-1
  • Debug State Cache Control Register (DBGDSCCR) on page 8-8

  • CP14 c1, Debug Status and Control Register (DBGDSCR) on page 8-9

  • Device Power-down and Reset Status Register (DBGPRSR) on page 8-27

  • Integration Mode Control Register (DBGITCTRL) on page 8-45

  • Claim Tag Clear Register (DBGCLAIMCLR) on page 8-47

  • Lock Access Register (DBGLAR) on page 8-48

  • Lock Status Register (DBGLSR) on page 8-49

  • Authentication Status Register (DBGAUTHSTATUS) on page 8-49

  • Device Type Register (DBGDEVTYPE) on page 8-50.

Corrected Table 10-1 footnotes Table 10.1.
Corrected byte address field entries Table 10.8.
Corrected interrupt signal descriptions Table A.3.
Extended AXI USER descriptions

Table C.3. Differences between issue B and issue C
ChangeLocation
Removed 2.8.1 LE and BE-8 accesses on a 64-bit wide bus .-
Removed Chapter 4 Unaligned and Mixed-Endian Data Access Support .-
Removed the power management signal BISTSCLAMP.-
Added dynamic high level clock gating .Dynamic high level clock gating on page 2-9
Updated TLB information .Table 1-1 on page 1-10, Table 4-10 on page 4-15, Table 4-37 on page 4-44
Shortened ID_MMF3[15:12] description .Memory Model Features Register 3 on page 4-49
Updated ACTLR to include reference to PL310 optimizations.Auxiliary Control Register on page 4-64
Added information about a second replacement strategy. Selection done by SCTLR.RR bit.System Control Register
Extended event information .Cortex-A9 specific events on page 4-32
Added DEFLAGS[6:0] DEFLAGS[6:0] on page 4-37, Performance monitoring signals
Added Power Control Register description Power Control Register on page 4-63
Added PL310 optimizations to L2 memory interface descriptionOptimized accesses to the L2 memory interface
Added watchpoint address maskingWatchpoint Control Registers
Added debug request restart diagram.Effects of resets on debug registers
Added CPUCLKOFF information Table A.4,Unregistered signals on page B-3
Added DECLKOFF information Table A.4,Unregistered signals on page B-3
Added MAXCLKLATENCY[2:0] information Configuration signals
Extended PMUEVENT bus description Performance monitoring signals
Added PMUSECURE and PMUPRIV Performance monitoring signals
Updated description of serializing behavior of DMB Serializing instructions

Table C.4. Differences between issue C and issue D
ChangeLocation
Included Preload Engine (PE) in block diagram Figure 1.1
Amended interrupt signals
Clarified Data Engine optionsData Engine
Clarified system design componentsSystem design components
Clarified Compliance Compliance
Added PE to featuresFeatures
Included PE and PE FIFO size in configurable options Configurable options
Clarified NEON SIMD and FPU options Table 1.1
Added Test Features section Test features
2.1.3 PTM interface rewordedPerformance monitoring
2.1.5 Virtualization of interrupts addedVirtualization of interrupts
Included NEON SIMD clock gating in power control description Power Control Register
Replaced nDERESET with nNEONRESET Reset modes
Added nWDRESET
Added nPERIPHRESET
Changed voltage domain boundaries and descriptionFigure 2.4
2.5.4 Date Engine logic reset replacedMPE SIMD logic reset
Cortex-A9 input signals DECLAMP removed, level shifters reference removedCommunication to the power management controller
Table 3-1 J and T bit encoding removed-
The Jazelle extension on page 3-3 movedThe Jazelle Extension
NEON technology on page 3-4 renamed and rewrittenAdvanced SIMD architecture
3.4 Processor operating states removed-
3.5 Data types removed-
Multiprocessing Extensions section addedMultiprocessing Extensions
3.6 Memory formats renamed and movedMemory model
3.8 Security extensions overview renamed and movedSecurity Extensions architecture
Removed content, tables and figures from 4.1 that duplicates ARM Architecture Reference Manual material About system control
4.2 Duplicates of ARM Architecture Reference Manual material removed, section renamedRegister summary
4.3 Duplicates of ARM Architecture Reference Manual material removed, section renamedRegister descriptions
Footnote e removedTable 4.8
Preload Engine registers addedCP15 c11 register summary
-PLE ID Register
-PLE Activity Status Register
-PLE FIFO Status Register
-Preload Engine User Accessibility Register
-Preload Engine Parameters Control Register
4.4 CP14 Jazelle registers and 4.5 CP14 Jazelle register descriptions in a new chapterChapter 5 Jazelle DBX registers
Chapter 5 Memory Management Unit, 5.6 MMU software-accessible registers section removed-
Level 1 Memory System chapter, Cortex-A9 cache policies section removed-
Prefetch hint to the L2 memory interface, description re-written and extendedPrefetch hint to the L2 memory interface
Clarifications of BRESP and cache controller behaviorEarly BRESP
Write full line of zeros, signal name corrected to AWUSERM0[7] Write full line of zeros
Speculative coherent requests section addedSpeculative coherent requests
Removed sentence about tying unused bits of PARITYFAIL HIGH Parity error support
Added PE description Chapter 9 Preload Engine
Added PMU description Chapter 11 Performance Monitoring Unit
Debug chapter, About debug systems removed-
Debug chapter, Debugging modes removed-
Duplicates of ARM Architecture Reference Manual material removed-
External debug interface, description of PADDRDBG[12:0] addedExternal debug interface
Debug APB interface section addedDebug APB interface
Amended and extended signals descriptions, source destination column addedAppendix A Signal Descriptions
PMUEVENT[46] description correctedTable A.17
PMUEVENT[47] description corrected
Removed AC Characteristics Appendix -

No differences between issue D and issue E.

Differences between issue D and issue F.

Table C.5. Differences between issue D and issue F
ChangeLocation
PL310 renamed L2C-310Throughout the book
VFPv3 corrected to VFPv3 D-32Media Processing Engine
Cortex-A9 FPU hardware description rewritten for clarityFloating-Point Unit
SCU description extendedCortex-A9 variants
Dynamic branch prediction description addedDynamic branch prediction
Final paragraph removedEnergy efficiency features
WFI/WFE corrected to StandbyTable 2.2
Renamed and rewritten for clarityStandby modes
Dormant mode clamping information removedDormant mode
IEM support renamed and rewritten Power domains
Repeated material removedAbout the programmers model
Debug register description correctedTable 4.1

Main ID Register values for r2p1 and r2p2 added

Table 4.2
Debug register name correctedTable 4.2
Descriptions clarified and footnote added.Table 4.4
Purpose description extendedCache Size Identification Register
System Control Register value corrected. Footnotes amended.Table 4.8
Bit[17] function correctedTable 4.9
Footnote d correctedTable 4.33
Purpose description extendedPower Control Register
Configurations description correctedConfiguration Base Address Register
Chapter renamedChapter 5 Jazelle DBX registers
6.1 application specific corrected to address space specificAbout the MMU
Unified Main TLB description clarifiedMemory Management Unit
Duplicate information about page sizes removed
ASID description corrected and extended. Cross-reference added.
TLB match process duplicate information about page sizes removedTLB match process
Synchronous and asynchronous aborts incorrect cross-reference removedSynchronous and asynchronous aborts
Cache features cross-reference correctedCache features
Implementation information removed
Return stack predictions ARM or Thumb state replaced by instruction stateReturn stack predictions
DSB section addedAbout DSB
AXI master 0 interface attributes corrections to valuesTable 8.1
Debug chapter moved to before PMU chapter 
Figure redrawnFigure 10.1
Corrections to bit formatTable 10.1
Footnote about CLUSTERID values addedTable 10.10
Value column addedTable 10.11
DBGCPUDONE description extendedDBGCPUDONE
PMU management registers section addedPMU management registers
Signal descriptions extended.Configuration signals
Signal descriptions extended, information repeated from AXI removedTable A.8
AWBURSTM0[1:0]
AWLENM0[3:0]
AWLOCKM0[1:0]
Signal descriptions extended, information repeated from AXI removedTable A.11
ARLENM0[3:0]
ARLOCKM0[1:0]
Title changedAXI Master1 signals instruction accesses
Information repeated from AXI removedTable A.14
ARLENM1[3:0] 
PMUEVENT[46] and PMUEVENT[47] correctedTable A.17
Introduction reduced. Note about DSB behavior added.Serializing instructions