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10.5.4. External debug request interface

The following sections describe the external debug request interface signals:


This signal generates a halting debug event, that is, it requests the processor to enter debug state. When this occurs, the DSCR[5:2] method of debug entry bits are set to b0100. When EDBGRQ is asserted, it must be held until DBGACK is asserted. Failure to do so leads to Unpredictable behavior of the processor.


The processor asserts DBGACK to indicate that the system has entered debug state. It serves as a handshake for the EDBGRQ signal. The DBGACK signal is also driven HIGH when the debugger sets the DSCR[10] DbgAck bit to 1.


DBGCPUDONE is asserted when the core has completed a Data Synchronization Barrier (DSB) as part of the entry procedure to debug state.

The processor asserts DBGCPUDONE only after it has completed all Non-debug state memory accesses. Therefore the system can use DBGCPUDONE as an indicator that all memory accesses issued by the processor result from operations performed by a debugger.

Figure 10.5 shows the Cortex-A9 connections specific to debug request and restart and the CoreSight pins.

Figure 10.5. Debug request restart-specific connections

Figure 10.5. Debug request restart-specific connections


The COMMRX and COMMTX output signals enable interrupt-driven communications over the DTR. By connecting these signals to an interrupt controller, software using the debug communications channel can be interrupted whenever there is new data on the channel or when the channel is clear for transmission.

COMMRX is asserted when the CP14 DTR has data for the processor to read, and it is deasserted when the processor reads the data. Its value is equal to the DBGDSCR[30] DTRRX full flag.

COMMTX is asserted when the CP14 is ready for write data, and it is deasserted when the processor writes the data. Its value equals the inverse of the DBGDSCR[29] DTRTX full flag.

Memory mapped accesses, DBGROMADDR, and DBGSELFADDR

Cortex-A9 processors have a memory-mapped debug interface. Cortex-A9 processors can access the debug and PMU registers by executing load and store instructions going through the AXI bus.

DBGROMADDR gives the base address for the ROM table which locates the physical addresses of the debug components.

DBGSELFADDR gives the offset from the ROM table to the physical addresses of the registers owned by the processor itself.