You copied the Doc URL to your clipboard.

11.3. Performance monitoring events

The Cortex-A9 processor implements the architectural events described in the ARM Architecture Reference Manual, with the exception of:


Memory-reading instruction architecturally executed


Procedure return, other than exception return, architecturally executed.

For events and the corresponding PMUEVENT signals, see Table A.18.

The PMU provides an additional set of Cortex-A9 specific events.