You copied the Doc URL to your clipboard.

11.2. PMU management registers

The PMU management registers define the standardized set of registers that is implemented by all CoreSight components. These registers are described in this section. The cp14 interface must be used to access these registers.

Table 11.2 shows the contents of the Management registers for the Cortex-A9 debug unit.

Table 11.2. PMU Management registers
OffsetRegister numberAccessMnemonicDescription
0xD00-0xDFC832-895RO-Processor ID Registers.
0xE00-0xEF0854-956--RAZ.
0xF00960RWITCTRL-
0xF04-0xF9C961-999RAZ-Reserved for Management Register expansion.
0xFA01000RWCLAIMSET-
0xFA41001RWCLAIMCLR-
0xFA8-0xFBC1002-1003--RAZ.
0xFB01004WOLOCKACCESS-
0xFB4 ROLOCKSTATUS-
0xFB8 ROAUTHSTATUS-
0xFBC-0xFC41007-1009--RAZ.
0xFC81010RODEVIDDevice Identifier.
0xFCC1011RODEVTYPE-
0xFD0-0xFFC1012-1023R-CoreSight Identification Registers.