This section shows summary tables of the register allocation and reset values of the system control coprocessor, grouped by the primary CP15 register number, CRn, used to access the register.
In the summaries of the registers in each CRn group:
CRn is the register number within CP15
Op1 is the Opcode_1 value for the register
CRm is the operational register
Op2 is the Opcode_2 value for the register.
Reset is the reset value of the register.
All system control coprocessor registers are 32 bits wide, except for the Program New Channel operation described in PLE Program New Channel operation. Reserved registers are RAZ/WI.
This section does not reproduce information about registers already described in the ARM Architecture Reference Manual. This chapter describes the implementation-defined control coprocessor registers.