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4.3.4. Cache Size Identification Register

The CCSIDR characteristics are:


Provides information about the architecture of the caches selected by CSSELR.

Usage constraints

The CCSIDR is:

  • only accessible in privileged modes.

  • common to the Secure and Non-secure states.


Available in all configurations.


See the register summary in Table 4.2.

Figure 4.3 shows the CCSIDR bit assignments.

Figure 4.3. CCSIDR bit assignments

Figure 4.3. CCSIDR bit assignments

Table 4.5 shows how the CSSIDR bit assignments.

Table 4.5. CCSIDR bit assignments



Indicates support available for Write-Through:

0 = Write-Through support not available

1 = Write-Through support available.



Indicates support available for Write-Back:

0 = Write-Back support not available

1 = Write-Back support available.



Indicates support available for read allocation:

0 = Read allocation support not available

1 = Read allocation support available.



Indicates support available for write allocation:

0 = Write allocation support not available

1 = Write allocation support available.



Indicates number of sets.

0x7F = 16KB cache size

0xFF = 32KB cache size

0x1FF = 64KB cache size.



Indicates number of ways.

b0000000011. Four ways.



Indicates number of words.

b001 = Eight words per line.

To access the CCSIDR, use:

MRC p15, 1, <Rd>, c0, c0, 0; Read current Cache Size Identification Register

If the CSSELR reads the instruction cache values, then bits[31:28] are b0010.

If the CSSELR reads the data cache values, then bits[31:28] are b0111. See Cache Size Selection Register.