The PLEASR characteristics are:
Indicates whether the PLE engine is currently active.
- Usage constraints
The PLEASR is:
Common to Secure and Non-secure states
Accessible in User and Privileged modes, regardless of any configuration bit.
Available in all Cortex-A9 configurations regardless of whether a PLE is present or not.
See Table 4.24.
Figure 4.14 shows the PLEASR bit assignments.
Table 4.26 shows the PLEASR bit assignments.
PLE Channel running
1 = The Preload Engine is currently handling a PLE request.
To access the PLEASR, use:
MRC p15, 0, <Rt>, c11, c0, 2; Read PLEASR