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4.3.26. PLE ID Register

The PLEIDR characteristics are:

Purpose

Indicates whether the PLE is present or not and the size of its FIFO.

Usage constraints

The PLEIDR is:

  • Common to Secure and Non-secure states

  • Accessible in User and Privileged modes, regardless of any configuration bit.

Configurations

Available in all Cortex-A9 configurations regardless of whether a PLE is present or not.

Attributes

Figure 4.13 shows the PLEIDR bit assignments.

Figure 4.13. PLEIDR bit assignments

Figure 4.13. PLEIDR bit assignments

Table 4.25 shows the PLEIDR bit assignments.

Table 4.25. PLEIDR bit assignments
BitsNameFunction
[31:21]--
[20:16]PLE FIFO size

Permitted values are:

  • 5’b00000 indicates the PLE is not present

  • 5’b00100 indicates a PLE is present with a FIFO size of 4 entries

  • 5’b01000 indicates a PLE is present with a FIFO size of 8 entries

  • 5’b10000 indicates a PLE is present with a FIFO size of 16 entries.

[15:1]-RAZ.
[0]-1 indicates that the Preload Engine is present in the given configuration.

To access the PLEIDR, use:

MRC p15, 0, <Rt>, c11, c0, 0; Read PLEIDR