The Power Control Register characteristics are:
Enables you to set:
the clock latency for your implementation of the Cortex-A9 processor.
dynamic clock gating.
- Usage constraints
a read and write register in Secure state
a read-only register in Non-secure state
Available in all configurations.
See the register summary in Table 4.33.
Figure 4.19 shows the Power Control Register bit assignments.
Table 4.34 shows the Power Control Register bit assignments.
|[10:8]||Max clock latency||Samples the value present on the MAXCLKLATENCY pins on exit from reset. This value reflects an implementation specific parameter, and ARM recommends that the software does not modify it.|
|||Enable dynamic clock gating||Disabled at reset.|
To access the Power Control Register, use:
MRC p15,0,<Rd>,c15,c0,0; Read Power Control Register
MCR p15,0,<Rd>,c15,c0,0; Write Power Control Register