The TLBTR characteristics are:
Returns the number of lockable entries for the TLB
- Usage constraints
The TLBTR is:
common to the Secure and Non-secure states.
only accessible in privileged mode.
Available in all configurations.
See the register summary in Table 4.2.
Figure 4.1 shows the TLBTR bit assignments.
Table 4.3 shows the TLBTR bit assignments.
|[23:16]||ILsize||Specifies the number of instruction TLB lockable entries. For the Cortex-A9 processor this is 0.|
|[15:8]||DLsize||Specifies the number of unified or data TLB lockable entries. For the Cortex-A9 processor this is 4.|
|[7:2]||SBZ or UNP||-|
0 = TLB has 64 entries
1 = TLB has 128 entries.
Specifies if the TLB is unified, 0, or if there are separate instruction and data TLBs.
0 = The Cortex-A9 processor has a unified TLB.
To access the TLBTR, use:
MRC p15,0,<Rd>,c0,c0,3; returns TLB details