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4.2. Register summary

Table 4.1 shows all the CP15 system control registers, ordered by the parameters used to access the register:

  • the primary CP15 coprocessor register, CRn

  • the opcode_1 value

  • the secondary CP15 coprocessor register, CRm

  • the opcode_2 value.

The table includes references to the summaries of the attributes of each CRn group of registers.

For registers described in the ARM Architecture Reference Manual see ARM Architecture Reference Manual, ARMv7-A and ARMv7-M editions.

Table 4.1. Summary of CP15 system control coprocessor registers
CRnNameRegister description
c0-CP15 c0 register summary

MIDR

Main ID Register, see the ARM Architecture Reference Manual

CTR

Cache Type Register, see the ARM Architecture Reference Manual

TCMTR

TCM Type Register, see the ARM Architecture Reference Manual

TLBTR

TLB Type Register

MPIDR

Multiprocessor Affinity Register

ID_PFR0Processor Feature Register 0, see the ARM Architecture Reference Manual
ID_PFR1Processor Feature Register 1, see the ARM Architecture Reference Manual
ID_DFR0Debug Feature Register , see the ARM Architecture Reference Manual
ID_MMFR0Memory Model Feature Register 0, see the ARM Architecture Reference Manual
ID_MMFR1Memory Model Feature Register 1, see the ARM Architecture Reference Manual
ID_MMFR2Memory Model Feature Register 2, see the ARM Architecture Reference Manual
ID_MMFR3Memory Model Feature Register 3, see the ARM Architecture Reference Manual
ID_ISAR0Instruction Set Attributes Register 0, see the ARM Architecture Reference Manual
c0ID_ISAR1Instruction Set Attributes Register 1, see the ARM Architecture Reference Manual
ID_ISAR2Instruction Set Attributes Register 2, see the ARM Architecture Reference Manual
ID_ISAR3Instruction Set Attributes Register 3, see the ARM Architecture Reference Manual
ID_ISAR4Instruction Set Attributes Register 4, see the ARM Architecture Reference Manual
CCSIDRCache Size Identification Register
CLIDRCache Level ID Register

AIDR

Auxiliary ID Register
CSSELRCache Size Selection Register
c1-CP15 c1 register summary

SCTLR

System Control Register

ACTLR

Auxiliary Control Register

CPACR

Coprocessor Access Control Register

SCRSecure Configuration Register, see the ARM Architecture Reference Manual
SDERSecure Debug Enable Register
NSACRNon-secure Access Control Register
VCRVirtualization Control Register
c2-CP15 c2 register summary

TTBR0

Translation Table Base Register 0, see the ARM Architecture Reference Manual

TTBR1

Translation Table Base Register 1, see the ARM Architecture Reference Manual

TTBCR

Translation Table Base Control Register, see the ARM Architecture Reference Manual
c3-CP15 c3 register summary

DACR

Domain Access Control Register, see the ARM Architecture Reference Manual

c4-CP15 c4, not used
c5-CP15 c5 register summary
DFSRData Fault Status Register, see the ARM Architecture Reference Manual

IFSR

Instruction Fault Status Register, see the ARM Architecture Reference Manual
ADFSRAuxiliary Data Fault Status Register, see the ARM Architecture Reference Manual
AIFSRAuxiliary Instruction Fault Status Register, see the ARM Architecture Reference Manual
c6-CP15 c6 register summary

DFAR

Data Fault Address Register, see the ARM Architecture Reference Manual

IFARInstruction Fault Address Register, see the ARM Architecture Reference Manual
c7-CP15 c7 register summary
ICIALLUISSee the ARM Architecture Reference Manual
BPIALLIS
PAR
ICIALLU
ICIMVAU
BPIALL
DCIMVAC
DCISW
V2PCWPR
DCCVAC
DCCSW
DCCVAU
DCCIMVAC
DCCISW
c8-CP15 c8 register summary
TLBIALLISSee the ARM Architecture Reference Manual
TLBIMVAIS
TLBIASIDIS
TLBIMVAAIS
TLBIALL
TLBIMVA
TLBIASID
TLBIMVAA
c9-CP15 c9 register summary
PMCRPerformance Monitor Control Register, see the ARM Architecture Reference Manual
PMCNTENSETCount Enable Set Register, see the ARM Architecture Reference Manual
PMCNTENCLRCount Enable Clear Register, see the ARM Architecture Reference Manual
PMOVSROverflow Flag Status Register, see the ARM Architecture Reference Manual
PMSWINCSoftware Increment Register, see the ARM Architecture Reference Manual
PMSELREvent Counter Selection Register, see the ARM Architecture Reference Manual
PMCCNTRCycle Count Register, see the ARM Architecture Reference Manual
PMXEVTYPEREvent Selection Register, see the ARM Architecture Reference Manual
PMXEVCNTRPerformance Monitor Count Registers, see the ARM Architecture Reference Manual
PMUSERENRUser Enable Register, see the ARM Architecture Reference Manual
PMINTENSETInterrupt Enable Set Register, see the ARM Architecture Reference Manual
PMINTENCLRInterrupt Enable Clear Register, see the ARM Architecture Reference Manual
c10-CP15 c10 register summary
-TLB Lockdown Register
PRRRPrimary Region Remap Register, see the ARM Architecture Reference Manual
NRRRNormal Memory Remap Register, see the ARM Architecture Reference Manual
c11-CP15 c11 register summary
PLEIDRPLE ID Register
PLEASRPLE Activity Status Register
PLEFSRPLE FIFO Status Register
PLEUARPreload Engine User Accessibility Register
PLEPCRPreload Engine Parameters Control Register
c12-CP15 c12 register summary
VBARVector Base Address Register, see the ARM Architecture Reference Manual
MVBARMonitor Vector Base Address Register, see the ARM Architecture Reference Manual
ISRInterrupt Status Register, see the ARM Architecture Reference Manual
-Virtualization Interrupt Register
c13-CP15 c13 register summary
 FCSEIDRFCSE PID Register, see the ARM Architecture Reference Manual
 CONTEXTIDRContext ID Register, see the ARM Architecture Reference Manual
 TPIDRURWUser Read/Write Software Thread Register, see the ARM Architecture Reference Manual
 TPIDRUROUser Read Only Software Thread Register, see the ARM Architecture Reference Manual
 TPIDRPRW.Privileged Only Software Thread Register, see the ARM Architecture Reference Manual
c14-CP15 c14, not used
c15-CP15 c15 register summary
-Power Control Register
-NEON busy Register
-Configuration Base Address Register
-TLB lockdown operations