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5.3.1. Jazelle ID Register

The JIDR characteristics are:

Purpose

Enables software to determine the implementation of the Jazelle Extension provided by the processor.

Usage constraints

The JIDR is:

Configurations

Available in all configurations.

Attributes

See the register summary in Table 5.1.

Figure 5.1 shows the JIDR bit assignments.

Figure 5.1. JIDR bit assignments

Figure 5.1. JIDR bit assignments

Table 5.2 shows the JIDR bit assignments.

Table 5.2. JIDR bit assignments
BitsNameFunction
[31:28]ArchThis uses the same architecture code that appears in the Main ID register.
[27:20]DesignContains the implementer code of the designer of the subarchitecture.
[19:12]SArchMajorThe subarchitecture code.
[11:8]SArchMinorThe subarchitecture minor code.
[7]-RAZ.
[6]TrTbleFrmIndicates the format of the Jazelle Configurable Opcode Translation Table Register.
[5:0]TrTbleSzIndicates the size of the Jazelle Configurable Opcode Translation Table Register.

To access the JIDR, read the CP14 register with:

MRC p14, 7, <Rd>, c0, c0, 0; Read Jazelle Identity Register

Write operation of the JIDR

A write to the JIDR clears the translation table. This has the effect of making all configurable opcodes executed in software only. See Jazelle Configurable Opcode Translation Table Register.

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