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5.2. CP14 Jazelle register summary

In the Cortex-A9 implementation of the Jazelle Extension:

  • Jazelle state is supported.

  • The BXJ instruction enters Jazelle state.

Table 5.1 shows the CP14 Jazelle registers. For all Jazelle register accesses, CRm and Op2 are zero. All Jazelle registers are 32 bits wide.

Table 5.1. CP14 Jazelle registers summary
70Jazelle ID Register (JIDR)RW[a]


Jazelle ID Register
71Jazelle OS Control Register (JOSCR)RW-Jazelle Operating System Control Register
72Jazelle Main Configuration Register (JMCR)RW-Jazelle Main Configuration Register
73Jazelle Parameters RegisterRW-Jazelle Parameters Register
74Jazelle Configurable Opcode Translation Table RegisterWO-Jazelle Configurable Opcode Translation Table Register

[a] See Write operation of the JIDR for the effect of a write operation.

See the ARM Architecture Reference Manual for information about the Jazelle Extension.

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