The L1 instruction side memory system provides an instruction stream to the Cortex-A9 processor. To increase overall performance and to reduce power consumption, it contains the following functionality:
dynamic branch prediction
Figure 7.1 shows this.
The ISide comprises the following:
- The Prefetch Unit (PFU)
The Prefetch Unit implements a 2-level prediction mechanism, comprising:
a 2-way BTAC of 512 entries organized as 2-way x 256 entries implemented in RAMs
a Global History Buffer (GHB) containing 4096 2-bit predictors implemented in RAMs
a return stack with eight 32-bit entries.
The prediction scheme is available in ARM state, Thumb state, ThumbEE state, and Jazelle state. It is also capable of predicting state changes from ARM to Thumb, and from Thumb to ARM. It does not predict
any other state changes
any instruction that changes the mode of the processor.
- Instruction Cache Controller
The instruction cache controller fetches the instructions from memory depending on the program flow predicted by the prefetch unit.
The instruction cache is 4-way set associative. It comprises the following features:
configurable sizes of 16KB, 32KB, or 64KB
Virtually Indexed Physically Tagged (VIPT)
64-bit native accesses to provide up to four instructions per cycle to the prefetch unit
Security Extensions support
no lockdown support.