If your configuration implements parity error support, the features are as follows:
the parity scheme is even parity. For byte 0000000 parity is 0.
each RAM in the design generates parity information. As a general rule each RAM byte generates one parity bit. Where RAM bit width is not a multiple of eight, the remaining bits produce one parity bit.
There is also support for parity bit-writable data.
RAM arrays in a design with parity support store parity information alongside the data in the RAM banks. As a result RAM arrays are wider when your design implements parity support.
The Cortex-A9 logic includes the additional parity generation logic and the parity checking logic.
Figure 7.2 shows the parity support design features and stages. In stages 1 and 2 RAM writes and parity generation take place in parallel. RAM reads and parity checking take place in parallel in stages 3 and 4.
The output signals PARITYFAIL[7:0] report parity errors. Typically, PARITYFAIL[7:0] reports parity errors three clock cycles after the corresponding RAM read.
This is not a precise error detection scheme. Designers can implement a precise error detection scheme by adding address register pipelines for RAMs. It is the responsibility of the designer to correctly implement this logic.