The PLEPCR characteristics are:
Contains PLE control parameters, available only in Privilege modes, to limit the issuing rate and transfer size of the PLE.
- Usage constraints
The PLEPCR is:
only accessible in privileged mode
common to Secure and Non-secure states
NSACR.PLE controls Non-secure accesses.
Only available in configurations where the Preload Engine is present, otherwise an Undefined Instruction exception is taken.
See Table 4.12.
Figure 4.19 shows the PLEPCR bit assignments.
Table 4.46 shows the PLEPCR bit assignments.
|[29:16]||Block size mask|
Permits Privilege modes to limit the maximum block size for PLE transfers.
The transferred block size is:
(Block size) & (Block size mask).
For example, a block size mask of 14’b11111111111111 authorizes the transfer of block sizes with the maximum value of 16k * 4 bytes. A block size mask of 14’b00000000000000 limits block sizes to 1 * 4 bytes.
|[15:8]||Block number mask|
Permits Privilege modes to limit the maximum number of blocks for a single PLE transfer.
The transferred block number is:
(Block number) & (Block number mask).
For example, a block number mask of 8’b11111111 authorizes the transfer of a maximum possible number of 256 blocks. A block number mask of 8’b00000000 limits the transfer to only one block of data.
|[7:0]||PLE wait states|
Permit Privilege modes to limit the issuing rate of PLD requests performed by the PLE engine to prevent saturation of the external memory bandwidth.
PLE wait states specifies the number of cycles inserted between two PLD requests performed by the PLE engine.
When PLE wait states is 8’b11111111, the PLE engine can issue one PLD request, a cache line, every 256 cycles.
When PLE wait states is 8’b000000000, the PLE engine can issue one PLD request every cycle.
To access the PLEPCR, read or write the CP15 register with:
MCR p15, 0, <Rt>, c11, c1, 1; Read PLEPCR MRC p15, 0, <Rt>, c11, c1, 1; Write PLEPCR