The SCTLR characteristics are:
Provides control and configuration of:
memory alignment and endianness
memory protection and fault behavior
MMU and cache enables
interrupts and behavior of interrupt latency
location for exception vectors
program flow prediction.
- Usage constraints
The SCTLR is:
Only accessible in privileged modes.
Partially banked. Table 4.35 shows banked and secure modify only bits.
Available in all configurations.
See the register summary in Table 4.3.
Figure 4.8 shows the SCTLR bit assignments.
Table 4.35 shows the SCTLR bit assignments.
Thumb exception enable:
0 = exceptions including reset are handled in ARM state
1 = exceptions including reset are handled in Thumb state.
The TEINIT signal defines the reset value.
Access Flag enable bit:
0 = Full access permissions behavior. This is the reset value. The software maintains binary compatibility with ARMv6K behavior.
1 = Simplified access permissions behavior. The Cortex-A9 processor redefines the AP bit as an access flag.
The TLB must be invalidated after changing the AFE bit.
This bit controls the TEX remap functionality in the MMU:
0 = TEX remap disabled. This is the reset value.
1 = TEX remap enabled.
Non-maskable FIQ support.
The bit cannot be configured by software.
The CFGNMFI signal defines the reset value.
Determines how the E bit in the CPSR is set on an exception:
0 = CPSR E bit is set to 0 on an exception
1 = CPSR E bit is set to 1 on an exception.
This value also indicates the endianness of the translation table data for translation table lookups.
0 = little-endian
1 = big-endian.
The CFGEND signal defines the reset value.
|||RR||Secure modify only|
Replacement strategy for the instruction cache, the BTAC, and the instruction and data micro TLBs. This bit is read/write in Secure state and read-only in Non-secure state:
0 = Random replacement. This is the reset value.
1 = Round-robin replacement.
Vectors bit. This bit selects the base address of the exception vectors:
0 = Normal exception
vectors, base address
= High exception vectors, Hivecs, base address
At reset the value for the secure version if this bit is taken from VINITHI.
Determines if instructions can be cached at any available cache level:
0 = Instruction caching disabled at all levels. This is the reset value.
1 = Instruction caching enabled.
Enables program flow prediction:
0 = Program flow prediction disabled. This is the reset value.
1 = Program flow prediction enabled.
SWP/SWPB enable bit:
0 = SWP and SWPB are undefined.This is the reset value.
1 = SWP and SWPB perform normally.
Determines if data can be cached at any available cache level:
0 = Data caching disabled at all levels. This is the reset value.
1 = Data caching enabled.
Enables strict alignment of data to detect alignment faults in data accesses:
0 = Strict alignment fault checking disabled. This is the reset value.
1 = Strict alignment fault checking enabled.
Enables the MMU:
0 = MMU disabled. This is the reset value.
1 = MMU enabled.
Attempts to read or write the SCTLR from secure or Non-secure User modes result in an Undefined Instruction exception.
Attempts to write to this register in secure privileged mode when CP15SDISABLE is HIGH result in an Undefined Instruction exception.
Attempts to write secure modify only bits in non-secure privileged modes are ignored.
Attempts to read secure modify only bits return the secure bit value.
Attempts to modify read-only bits are ignored.
To access the SCTRL, read or write the CP15 register with:
MRC p15, 0,<Rd>, c1, c0, 0; Read SCTLR MCR p15, 0,<Rd>, c1, c0, 0; Write SCTLR