TLB lockdown operations enable saving or restoring lockdown entries in the TLB. Table 4.50 shows the defined TLB lockdown operations.
|Select Lockdown TLB Entry for Read||Main TLB Index|
|Select Lockdown TLB Entry for Write||Main TLB Index|
|Read Lockdown TLB VA Register||Data|
|Write Lockdown TLB VA Register||Data|
|Read Lockdown TLB PA Register||Data|
|Write Lockdown TLB PA Register||Data|
|Read Lockdown TLB attributes Register||Data|
|Write Lockdown TLB attributes Register||Data|
The Select Lockdown TLB entry for a read operation is used to select the entry that the data read by a read Lockdown TLB VA/PA/attributes operations are coming from. The Select Lockdown TLB entry for a write operation is used to select the entry that the data write Lockdown TLB VA/PA/attributes data are written to. The TLB PA register must be the last written or read register when accessing TLB lockdown registers. Figure 4.24 shows the bit assignment of the index register used to access the lockdown TLB entries.
Figure 4.25 shows the bit arrangement of the TLB VA Register format.
Table 4.51 shows the TLB VA Register bit assignments.
Virtual page number.
Bits of the virtual page number that are not translated as part of the page table translation because the size of the tables is unpredictable when read and SBZ when written.
Memory space identifier.
Figure 4.26 shows the bit arrangement of the memory space identifier.
Figure 4.27 shows the TLB PA Register bit assignment.
Table 4.52 describes the functions of the TLB PA Register bits.
Physical Page Number.
Bits of the physical page number that are not translated as part of the page table translation are unpredictable when read and SBZP when written.
b00 = 16MB Supersection
b01 = 4KB page
b10 = 64KB page
b11 = 1MB section.
All other values are reserved.
b000 = All accesses generate a permission fault
b001 = Supervisor access only, User access generates a fault
b010 = Supervisor read/write access, User write access generates a fault
b011 = Full access, no fault generated
b100 = Reserved
b101 = Supervisor read-only
b110 = Supervisor/User read-only
b111 = Supervisor/User read-only.
Indicates that this entry is locked and valid.
Figure 4.28 shows the bit assignments of the TLB Attributes Register.
Table 4.53 shows the TLB Attributes Register bit assignments. The Cortex-A9 processor does not support subpages.
|[10:7]||Domain||Domain number of the TLB entry.|
|||XN||Execute Never attribute.|
Region type encoding. See the ARM Architecture Reference Manual.
This is a single interruptible operation that invalidates all TLB entries that match the provided Address Space Identifier (ASID) value. This function invalidates locked entries. Entries marked as global are not invalidated by this function.
In the Cortex-A9 processor, this operation takes several cycles
to complete and the instruction is interruptible. When interrupted
the r14 state is set to indicate that the
has not executed. Therefore, r14 points to the address of the
4. The interrupt routine then automatically restarts at the
If this operation is interrupted and later restarted, any entries
fetched into the TLB by the interrupt that uses the provided ASID
are invalidated by the restarted invalidation.