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B.4. Multiplication instructions

Table B.4 shows the cycle timings for multiplication instructions.

Table B.5. Multiplication instruction cycle timings
Instruction Cycles Result latency

MUL(S), MLA(S)

24

SMULL(S), UMULL(S), SMLAL(S), UMLAL(S)

3

4 for the first written register

5 for the second written register

SMULxy, SMLAxy, SMULWy, SMLAWy

13

SMLALxy

2

3 for the first written register

4 for the second written register

SMUAD, SMUADX, SMLAD, SMLADX, SMUSD, SMUSDX, SMLSD, SMLSDX

13

SMMUL, SMMULR, SMMLA, SMMLAR, SMMLS, SMMLSR

24

SMLALD, SMLALDX, SMLSLD, SMLDLDX

2

3 for the first written register

4 for the second written register

UMAAL

3

4 for the first written register

5 for the second written register


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