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10.6. Debug management registers

The Debug management registers define the standardized set of registers that is implemented by all CoreSight components. This section describes these registers.

You can access these registers:

  • through the internal CP14 interface

  • through the APB using the relevant offset when PADDRDBG[12]=0

See the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition for additional information about these registers.

Table 10.9 shows the contents of the management registers for the Cortex-A9 debug unit.

Table 10.9. Debug management registers
Register numberOffsetNameCRnOp1CRmOP2TypeDescription
9600xF00DBGITCTRLc70c04RAZ/WIIntegration Mode Control Register
961-9990xF04- 0xF9C-    RAZReserved
10000xFA0DBGCLAIMSETc70c86RWClaim Tag Set Register
10010xFA4DBGCLAIMCLRc70c96RWClaim Tag Clear Register
1002- 10030xFA8-0xFBC-    RAZReserved
10040xFB0DBGLARc70c126WOLock Access Register
10050xFB4DBGLSRc70c136ROLock Status Register
10060xFB8DBGAUTHSTATUSc70c146ROAuthentication Status Register
1007- 10090xFBC-0xFC4-    RAZReserved
10100xFC8DBGDEVIDc70c27RAZ/WIDebug Device ID Register
10110xFCCDBGDEVTYPEc70c37RODevice Type Register
1012- 10230xFD0-0xFECDBGPIDc70c4-c87ROSee Peripheral Identification Registers.
1020- 10230xFF0-0xFFCDBGCID c70c12-c157ROSee Component Identification Registers