The system can access memory-mapped debug registers through the Cortex-A9 APB slave port.
This APB slave interface supports 32-bits wide data, stalls, slave-generated aborts, and 11 address bits [12:2] mapping 2x4KB of memory. bit  of PADDRDBG[12:0] selects which of the components is accessed:
The PADDRDBG31 signal indicates to the processor the source of the access.
See Appendix A Signal Descriptions for a complete list of the external debug signals.
Figure 10.5 shows the external debug interface signals.