The following sections describe the external debug request interface signals:
This signal generates a halting debug event, to request the processor to enter debug state. When this occurs, the DSCR[5:2] method of debug entry bits are set to b0100. When EDBGRQ is asserted, it must be held until DBGACK is asserted. Failure to do so leads to unpredictable behavior of the processor.
DBGCPUDONE is asserted when the processor has completed a DSB as part of the entry procedure to debug state.
The processor asserts DBGCPUDONE only after it has completed all Non-debug state memory accesses. Therefore the system can use DBGCPUDONE as an indicator that all memory accesses issued by the processor result from operations performed by a debugger.
Figure 10.6 shows the Cortex-A9 connections specific to debug request and restart.
The COMMRX and COMMTX output signals enable interrupt-driven communications over the DTR. By connecting these signals to an interrupt controller, software using the debug communications channel can be interrupted whenever there is new data on the channel or when the channel is clear for transmission.
COMMRX is asserted when the CP14 DTR has data for the processor to read, and it is deasserted when the processor reads the data. Its value is equal to the DBGDSCR DTRRX full flag.
COMMTX is asserted when the CP14 is ready for write data, and it is deasserted when the processor writes the data. Its value ia equal to the inverse of the DBGDSCR DTRTX full flag.
The Cortex-A9 processor has a memory-mapped debug interface. The processor can access the debug and PMU registers by executing load and store instructions through the AXI bus.
DBGROMADDR gives the base address for the ROM table that locates the physical addresses of the debug components.
DBGSELFADDR gives the offset from the ROM table to the physical addresses of the processor registers.