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1.2. Cortex-A9 variants

Cortex-A9 processors can be used in both a uniprocessor configuration and multiprocessor configurations.

In the multiprocessor configuration, up to four Cortex-A9 processors are available in a cache-coherent cluster, under the control of a Snoop Control Unit (SCU), that maintains L1 data cache coherency.

The Cortex-A9 MPCore multiprocessor has:

  • up to four Cortex-A9 processors

  • an SCU responsible for:

    • maintaining coherency among L1 data caches

    • Accelerator Coherency Port (ACP) coherency operations

    • routing transactions on Cortex-A9 MPCore AXI master interfaces

    • Cortex-A9 uniprocessor accesses to private memory regions.

  • an Interrupt Controller (IC) with support for legacy ARM interrupts

  • a private timer and a private watchdog per processor

  • a global timer

  • AXI high-speed Advanced Microprocessor Bus Architecture version 3 (AMBA 3) L2 interfaces.

  • an Accelerator Coherency Port (ACP), that is, an optional AXI 64-bit slave port that can be connected to a DMA engine or a noncached peripheral.

See the Cortex-A9 MPCore Technical Reference Manual for more information.

The following system registers have Cortex-A9 MPCore uses:

Some PMU event signals have Cortex-A9 MPCore uses. See Performance monitoring signals.

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