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1.9. Product revisions

This section describes the differences in functionality between product revisions:


First release.


The only differences between the two revisions are:

  • r0p1 includes fixes for all known engineering errata relating to r0p0

  • r0p1 includes an upgrade of the micro TLB entries from 8 to 32 entries, on both the Instruction and Data side.

Neither of these changes affect the functionality described in this document.


Functional changes are:

  • r1p0 includes fixes for all known engineering errata relating to r0p1.

  • In r1p0 CPUCLKOFF and DECLKOFF enable control of Cortex-A9 processors during reset sequences. See Configuration signals.

    • In a multiprocessor implementation of the design there are as many CPUCLKOFF pins as there are Cortex-A9 processors.

    • DECLKOFF controls the data engine clock during reset sequences.

  • r1p0 includes dynamic high level clock gating of the Cortex-A9 processor. See Dynamic high level clock gating on page 2-8.

  • Extension of the Performance Monitoring Event bus. In r1p0, PMUEVENT is 52 bits wide:

    • Addition of Cortex-A9 specific events. See Table 2-2 on page 2-5.

    • Event descriptions extended. See Table 2-2 on page 2-5.

  • Addition of PMUSECURE and PMUPRIV. See Performance monitoring signals.

  • Main TLB options for 128 entries or 64 entries. See TLB Type Register.

  • DEFLAGS[6:0] added. See DEFLAGS[6:0] on page 4-37.

  • The power management signal BISTSCLAMP is removed.

  • The scan test signal SCANTEST is removed.

  • Addition of a second replacement strategy. Selection done by SCTLR.RR bit. See System Control Register.

  • Addition of PL310 cache controller optimization description. See Optimized accesses to the L2 memory interface.

  • Change to the serializing behavior of DMB. See Serializing instructions.

  • ID Register values changed to reflect correct revision.


Functional changes are:


No functional changes.


No functional changes. Documentation updates and corrections only. See Table C.5.


Addition of the REVIDR. See Revision ID register.


Functional changes are:

  • Addition of new hardware configuration options for the TLB, BTAC, GHB and Instruction micro TLB sizes. See Configurable options.

  • Enhanced data prefetching mechanism. See Data prefetching


No change.

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