The L1 memory system of the Cortex-A9 processor has a local
monitor. This is a 2-state, open and exclusive, state machine that
manages load/store exclusive (
accesses and clear exclusive (
You can use these instructions to construct semaphores, ensuring
synchronization between different processes running on the processor,
and also between different processors that are using the same coherent
memory locations for the semaphore.
A store exclusive can generate an MMU fault or cause the processor to take a data watchpoint exception regardless of the state of the local monitor. See Table 10.8.
See the ARM Architecture Reference Manual for more information about these instructions.
In cases where there is an intervening
STREX code sequence,
STR does not produce any effect
on the internal exclusive monitor. The local monitor is in the Exclusive
Access state after the
LDREX, remains in the
Exclusive Access state after the
STR, and returns
to the Open Access state only after the
In cases where the LDREX and STREX operations are of different sizes a check is performed to ensure that the tagged address bytes match or are within the size range of the store operation.
The granularity of the tagged address for an
is eight words, aligned on an 8-word boundary. This size is implementation-defined,
and as such, software must not rely on this granularity remaining
constant on other ARM cores.