BRESP answers on response channels must be returned to the master only when the last data has been sent by the master. The Cortex-A9 processor can also deal with BRESP answers returned as soon as address has been accepted by the slave, regardless of whether data is sent or not. This enables the Cortex-A9 processor to provide a higher bandwidth for writes if the slave can support the Early BRESP feature. The Cortex-A9 processor sets the AWUSER bit to indicate to the slave that it can accept an early BRESP answer for this access. This feature can optimize the performance of the processor, but the Early BRESP feature generates non-AXI compliant requests. When a slave receives a write request with AWUSER set, it can either give the BRESP answer after the last data is received, AXI compliant, or in advance, non-AXI compliant. The L2C-310 cache controller supports this non-AXI compliant feature.
The Cortex-A9 processor does not require any programming to enable this feature, that is always on by default.
You must program the L2 cache controller to benefit from this optimization. See the CoreLink Level 2 Cache Controller (L2C-310) Technical Reference Manual.