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6.1.1. Memory Management Unit

The MMU performs the following operations:

  • checking of Virtual Address and ASID

  • checking of domain access permissions

  • checking of memory attributes

  • virtual-to-physical address translation

  • support for four page (region) sizes

  • mapping of accesses to cache, or external memory

  • TLB loading for hardware and software.


The Cortex-A9 processor supports 16 access domains.


The Cortex-A9 processor implements a 2-level TLB structure. Four entries in the main TLB are lockable.


Main TLB entries can be global, or can be associated with particular processes or applications using Address Space Identifiers (ASIDs). ASIDs enable TLB entries to remain resident during context switches, avoiding the requirement of reloading them subsequently. See Invalidate TLB Entries on ASID Match.

System control coprocessor

TLB maintenance and configuration operations are controlled through a dedicated coprocessor, CP15, integrated within the processor. This coprocessor provides a standard mechanism for configuring the level one memory system.