When the processor generates a memory access, the MMU:
Performs a lookup for the requested virtual address and current ASID and security state in the relevant instruction or data micro TLB.
If there is a miss in the micro TLB, performs a lookup for the requested virtual address and current ASID and security state in the main TLB.
If there is a miss in the main TLB, performs a hardware translation table walk.
You can configure the MMU to perform hardware translation table walks in cacheable regions by setting the IRGN bits in the Translation Table Base Registers. If the encoding of the IRGN bits is write-back, then an L1 data cache lookup is performed and data is read from the data cache. If the encoding of the IRGN bits is write-through or non-cacheable then an access to external memory is performed.
The MMU might not find a global mapping, or a mapping for the selected ASID, with a matching Non-secure TLB ID (NSTID) for the virtual address in the TLB. In this case, the hardware does a translation table walk if the translation table walk is enabled by the PD0 or PD1 bit in the TTB Control Register. If translation table walks are disabled, the processor returns a Section Translation fault.
If the MMU finds a matching TLB entry, it uses the information in the entry as follows:
The access permission bits and the domain determine if the access is enabled. If the matching entry does not pass the permission checks, the MMU signals a memory abort. See the ARM Architecture Reference Manual for a description of access permission bits, abort types and priorities, and for a description of the IFSR and Data Fault Status Register (DFSR).
The memory region attributes specified in both the TLB entry and the CP15 c10 remap registers control the cache and write buffer, and determine if the access is
Secure or Non-secure
Shared or not
Normal memory, Device, or Strongly-ordered.
The MMU translates the virtual address to a physical address for the memory access.
If the MMU does not find a matching entry, a hardware table walk occurs.