In the Cortex-A9 processor, the VA and MVA are identical.
When the Cortex-A9 processor is executing in Non-secure state, the processor performs translation table lookups using the Non-secure versions of the Translation Table Base Registers. In this situation, any VA can only translate into a Non-secure PA.When it is in Secure state, the Cortex-A9 processor performs translation table lookups using the Secure versions of the Translation Table Base Registers. In this situation, the security state of any VA is determined by the NS bit of the translation table descriptors for that address.
Table 3.2 shows the address types in the processor system.
Translation Lookaside Buffers
Data cache is Physically Indexed Physically Tagged (PIPT)
Translates Virtual Address
to Physical Address
Instruction cache is Virtually Indexed Physically Tagged (VIPT)
This is an example of the address manipulation that occurs when the Cortex-A9 processor requests an instruction.
The Cortex-A9 processor issues the VA of the instruction as Secure or Non-secure VA according to the state the processor is in.
The instruction cache is indexed by the lower bits of the VA. The TLB performs the translation in parallel with the cache lookup. The translation uses Secure descriptors if the processor is in the Secure state. Otherwise it uses the Non-secure descriptors.
If the protection check carried out by the TLB on the VA does not abort and the PA tag is in the instruction cache, the instruction data is returned to the processor.
If there is a cache miss, the PA is passed to the AXI bus interface to perform an external access. The external access is always Non-secure when the processor is in the Non-secure state. In the Secure state, the external access is Secure or Non-secure according to the NS attribute value in the selected descriptor. In Secure state, both L1 and L2 table walks accesses are marked as Secure, even if the first level descriptor is marked as NS.
Secure L2 lookups are secure even if the L1 entry is marked Non-secure.