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3.7.1. Operating states

The processor has the following instruction set states controlled by the T bit and J bit in the CPSR.

ARM state

The processor executes 32-bit, word-aligned ARM instructions.

Thumb state

The processor executes 16-bit and 32-bit, halfword-aligned Thumb instructions.

Jazelle state

The processor executes variable length, byte-aligned Jazelle instructions.

ThumbEE state

The processor executes a variant of the Thumb instruction set designed as a target for dynamically generated code. This is code compiled on the device either shortly before or during execution from a portable bytecode or other intermediate or native representation.

The J bit and the T bit determine the instruction set used by the processor. Table 3.1 shows the encoding of these bits.

Table 3.1. CPSR J and T bit encoding
JTInstruction set state
00ARM
01Thumb
10Jazelle
11ThumbEE

Note

Transition between ARM and Thumb states does not affect the processor mode or the register contents. See the ARM Architecture Reference Manual for information on entering and exiting ThumbEE state.

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