This appendix describes the technical changes between released issues of this book.
Change | Location |
---|---|
Clarified Load/Store Unit and address generation. | Figure 1.1. |
Changed fast loop mode to small loop mode. |
|
Changed branch prediction to dynamic branch prediction. | |
Changed LI cache coherency to L1 data cache coherency. | Cortex-A9 variants. |
Corrected Processor Feature Register 0 reset value. | Table 4-29 on page 4-46. |
Made PMSWINC descriptions consistent. |
|
Updated MIDR bits [3:0] from 0 to 1. | Table 4-1 on page 4-5. |
Corrected ID_MMFR3 [23:20] bit value to 0x1 . | Table 4-42 on page 4-50. |
Corrected AFE bit description. | Table 4-51 on page 4-62. |
Corrected Auxiliary Control Register bit field. |
|
Corrected S parameter values. | Set/Way format on page 4-83. |
Made descriptions of bits [11], [10], and [8] consistent with table. | Figure 4-41 on page 4-87. |
Corrected description of event 0x68 ,
architecturally removed. | Table 4-80 on page 4-123. |
Corrected TLB lockdown entries number from 8 to 4. | c10, TLB Lockdown Register on page 4-134. |
Corrected A, I, and F bit descriptions. | c12, Interrupt Status Register on page 4-147. |
Changed number of micro TLB entries from 8 to 32. | Micro TLB. |
Removed repeated information about cache types. | Micro TLB. |
Amended IRGN bits description from TTBCR to TTBR0/TTRBR1. | Main TLB. |
Added note about invalidating the caches and BTAC before use. | About the L1 memory system. |
Added parity support scheme information section. | Parity error support. |
Listed and described L2 master interfaces, M0 and M1. | Cortex-A9 L2 interface. |
Added cross reference to DBSCR external description. Extended footnote to include reference to the DBSCR external view. | Table 10.1. |
Corrected DBGDSCR description with the addition of internal and external view descriptions. | CP14 c1, Debug Status and Control Register (DBGDSCR) on page 8-9. |
Re-ordered and extended MOE bits descriptions. | Table 8-2 on page 8-10. |
Added more cross-references from Table 10-1. |
|
Corrected Table 10-1 footnotes. | Table 10.1. |
Corrected byte address field entries. | Table 10.8. |
Corrected interrupt signal descriptions. | Table A.3. |
Extended AXI USER descriptions. |
Change | Location |
---|---|
Removed 2.8.1 LE and BE-8 accesses on a 64-bit wide bus. | - |
Removed Chapter 4 Unaligned and Mixed-Endian Data Access Support. | - |
Removed the power management signal BISTSCLAMP. | - |
Added dynamic high level clock gating. | Dynamic high level clock gating on page 2-9 |
Updated TLB information. | Table 1-1 on page 1-10, Table 4-10 on page 4-15, Table 4-37 on page 4-44 |
Shortened ID_MMF3[15:12] description. | Memory Model Features Register 3 on page 4-49 |
Updated ACTLR to include reference to PL310 optimizations. | Auxiliary Control Register on page 4-64 |
Added information about a second replacement strategy. Selection done by SCTLR.RR bit. | System Control Register |
Extended event information. | Cortex-A9 specific events on page 4-32 |
Added DEFLAGS[6:0]. | DEFLAGS[6:0] on page 4-37, Performance monitoring signals |
Added Power Control Register description. | Power Control Register on page 4-63 |
Added PL310 optimizations to L2 memory interface description. | Optimized accesses to the L2 memory interface |
Added watchpoint address masking. | Watchpoint Control Registers |
Added debug request restart diagram. | Effects of resets on debug registers |
Added CPUCLKOFF information. | Table A.4,Unregistered signals on page B-3 |
Added DECLKOFF information. | Table A.4,Unregistered signals on page B-3 |
Added MAXCLKLATENCY[2:0] information. | Configuration signals |
Extended PMUEVENT bus description. | Performance monitoring signals |
Added PMUSECURE and PMUPRIV. | Performance monitoring signals |
Updated description of serializing behavior
of DMB . | Serializing instructions |
Change | Location |
---|---|
Included Preload Engine (PE) in block diagram | Figure 1.1 |
Amended interrupt signals | |
Clarified data engine options | Data engine |
Clarified system design components | System design components |
Clarified Compliance | Compliance |
Added PE to features | Features |
Included PE and PE FIFO size in configurable options | Configurable options |
Clarified NEON SIMD and FPU options | Table 1.1 |
Added Test Features section | Test features |
Reworded the PTM interface section | Performance monitoring |
Added a new section for Virtualization of interrupts | Virtualization of interrupts |
Included NEON SIMD clock gating in power control description | Power Control Register |
Replaced nDERESET with nNEONRESET | Reset modes |
Added nWDRESET | |
Added nPERIPHRESET | |
Changed voltage domain boundaries and description | Figure 2.4 |
2.5.4 Date Engine logic reset replaced | MPE SIMD logic reset |
Cortex-A9 input signals DECLAMP removed, level shifters reference removed | Communication to the power management controller |
Table 3-1 J and T bit encoding removed | - |
The Jazelle extension on page 3-3 moved | The Jazelle Extension |
NEON technology on page 3-4 renamed and rewritten | Advanced SIMD architecture |
3.4 Processor operating states removed | - |
3.5 Data types removed | - |
Multiprocessing Extensions section added | Multiprocessing Extensions |
3.6 Memory formats renamed and moved | Memory model |
3.8 Security Extensions overview renamed and moved | Security Extensions architecture |
Removed content, tables and figures from 4.1 that duplicates ARM Architecture Reference Manual material | About system control |
4.2 Duplicates of ARM Architecture Reference Manual material removed, section renamed | Register summary |
4.3 Duplicates of ARM Architecture Reference Manual material removed, section renamed | Register descriptions |
Footnote e removed | Table 4.3 |
Preload Engine registers added | c11 registers |
- | PLE ID Register |
- | PLE Activity Status Register |
- | PLE FIFO Status Register |
- | Preload Engine User Accessibility Register |
- | Preload Engine Parameters Control Register |
4.4 CP14 Jazelle registers and 4.5 CP14 Jazelle register descriptions in a new chapter | Chapter 5 Jazelle DBX registers |
Chapter 5 Memory Management Unit, 5.6 MMU software-accessible registers section removed | - |
Level 1 Memory System chapter, Cortex-A9 cache policies section removed | - |
Prefetch hint to the L2 memory interface, description rewritten and extended | Prefetch hint to the L2 memory interface |
Clarifications of BRESP and cache controller behavior | Early BRESP |
Write full line of zeros, signal name corrected to AWUSERM0[7] | Write full line of zeros |
Speculative coherent requests section added | Speculative coherent requests |
Removed sentence about tying unused bits of PARITYFAIL HIGH | Parity error support |
Added PE description | Chapter 9 Preload Engine |
Added PMU description | Chapter 11 Performance Monitoring Unit |
Debug chapter, About debug systems removed | - |
Debug chapter, Debugging modes removed | - |
Duplicates of ARM Architecture Reference Manual material removed | - |
External debug interface, description of PADDRDBG[12:0] added | External debug interface |
Debug APB interface section added | Debug APB Interface |
Amended and extended signals descriptions, source destination column added | Appendix A Signal Descriptions |
PMUEVENT[46] description corrected | Table A.17 |
PMUEVENT[47] description corrected | |
Removed AC Characteristics Appendix | - |
No differences between issue D and issue E.
Change | Location |
---|---|
PL310 renamed L2C-310 | Throughout the book |
VFPv3 corrected to VFPv3 D-32 | Media Processing Engine |
Cortex-A9 FPU hardware description rewritten for clarity | Floating-Point Unit |
SCU description extended | Cortex-A9 variants |
Dynamic branch prediction description added | Dynamic branch prediction |
Final paragraph removed | Energy efficiency features |
WFI/WFE corrected to Standby | Table 2.2 |
Renamed and rewritten for clarity | Standby modes |
Dormant mode clamping information removed | Dormant mode |
IEM support renamed and rewritten | Power domains |
Repeated material removed | About the programmers model |
Debug register description corrected | Table 4.2 |
Main ID Register values for r2p1 and r2p2 added | Table 4.2 |
Debug register name corrected | Table 4.2 |
Descriptions clarified and footnote added. | Table 4.30 |
Purpose description extended | Cache Size Identification Register |
System Control Register value corrected, and footnotes amended | Table 4.3 |
Bit [17] function corrected | Table 4.35 |
Footnote d corrected | Table 4.15 |
Purpose description extended | Power Control Register |
Configurations description corrected | Configuration Base Address Register |
Chapter renamed | Chapter 5 Jazelle DBX registers |
6.1 application specific corrected to address space specific | About the MMU |
Unified Main TLB description clarified | Memory Management Unit |
Duplicate information about page sizes removed | |
ASID description corrected and extended, and cross-reference added | |
TLB match process duplicate information about page sizes removed | TLB match process |
Synchronous and asynchronous aborts incorrect cross-reference removed | Synchronous and asynchronous aborts |
Cache features cross-reference corrected | Cache features |
Implementation information removed | |
Return stack predictions ARM or Thumb state replaced by instruction state | Return stack predictions |
DSB section added | About DSB |
AXI master 0 interface attributes corrections to values | Table 8.1 |
Debug chapter moved to before PMU chapter | |
Figure redrawn | Figure 10.2 |
Corrections to bit format | Table 10.1 |
Footnote about CLUSTERID values added | Table 4.16 |
Value column added | Table 10.10 |
DBGCPUDONE description extended | DBGCPUDONE |
PMU management registers section added | PMU management registers |
Signal descriptions extended | Configuration signals |
Signal descriptions extended, information repeated from AXI removed | Table A.8 |
AWBURSTM0[1:0] | |
AWLENM0[3:0] | |
AWLOCKM0[1:0] | |
Signal descriptions extended, information repeated from AXI removed | Table A.11 |
ARLENM0[3:0] | |
ARLOCKM0[1:0] | |
Title changed | AXI Master1 signals instruction accesses |
Information repeated from AXI removed | Table A.14 |
ARLENM1[3:0] | |
PMUEVENT[46] and PMUEVENT[47] corrected | Table A.17 |
Introduction reduced, and note about DSB behavior
added. | Serializing instructions |
Change | Location | Affects |
---|---|---|
Update description of transition from standby to run mode | Standby modes | All revisions |
Addition of REVIDR- | c15 registers | r3p0 |
Revision ID register | r3p0 | |
Data cache no longer supports round robin replacement policy | From r2p0 | |
Update description of accessing the Jazelle Configurable Opcode Translation Table Register | Jazelle Configurable Opcode Translation Table Register | All revisions |
Clarified implementation-defined aspect of invalidating TLBs | About the L1 memory system | All revisions |
Added information about cache policies | Cortex-A9 behavior for Normal Memory Cacheable memory regions | All revisions |
AWUSERM0[8:0] encodings table corrected | Table 8.5 | All revisions |
Update the introduction to debug register features | Debug register features | All revisions |
Remove reference to PMU registers from Debug chapter | All revisions | |
Update introduction to debug register summary | All revisions | |
Remove reference to DBGDSCCR | All revisions | |
Update description of BVR | Table 10.5 | All revisions |
Move debug management registers information from debug registers summary to debug management registers | All revisions | |
Update description of debug management registers | Debug management registers | All revisions |
Update description of DBGITCTRL and DBGDEVID registers | Table 10.9 | All revisions |
Update description of external debug interface | External debug interface | All revisions |
Update introduction to PMU register summary | PMU register summary | All revisions |
Remove reference to Processor ID Registers from Debug chapter | Table 11.1 | All revisions |
Update descriptions of PMICTRL and PMDEVID | Table 11.2 | All revisions |
Update description of PMU management registers | PMU management registers | All revisions |
Update description of performance monitoring events | Performance monitoring events | All revisions |
Updated description of PENABLEDBG signal | Table A.26 | All revisions |
CoreLink Level 2 Cache Controller renamed | Throughout document | All revisions |
Change | Location | Affects |
---|---|---|
Updated hardware configuration options for the TLB, BTAC and GHB sizes, and the number of entries in the Instruction micro TLB. | Table 1.1 | r4p0 |
Update SCR register description | c1 registers | All revisions |
Update PRRR and NMRR register descriptions | c10 registers | All revisions |
Change to revision number | Table 4.28 | r4p0 |
Updated TLB Type Register description | TLB Type Register | r4p0 |
Updated TLB description | About the MMU | r4p0 |
Main TLB | r4p0 | |
Updated BTAC description | About the L1 instruction side memory system | r4p0 |
Added description of an enhanced data prefetching mechanism. | Data prefetching | r4p0 |
Updated parity error support description | Parity error support | r4p0 |
Updated description of PLE Program New Channel operation | PLE Program New Channel operation | All revisions |
Updated heading of table describing Meaning of BVR as specified by BCR bits [22:20] | Table 10.5 | All revisions |
Updated description of PMU architectural events | Table 11.5 | All revision |
Added new PMU events | Table 11.6 | r4p0 |
Updated description of WFE and WFI standby signals | Table A.6 | All revisions |
Updated description of path optimization | Load and store instructions | All revisions |
Change | Location | Affects |
---|---|---|
Revision number changes only. | Main ID Register | r4p1 |