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A.9. Exception flags signal

Table A.19 shows the DEFLAGS signal.

Table A.19. DEFLAGS signal
NameI/ODestinationDescription
DEFLAGS[6:0]OException monitoring unit

Data engine output flags. Only implemented if the Cortex-A9 processor includes a Data engine, either an MPE or FPU.

If the DE is MPE:

  • Bit [6] gives the value of FPSCR[27]

  • Bit [5] gives the value of FPSCR[7]

  • Bits [4:0] give the value of FPSCR[4:0].

If the DE is FPU:

  • Bit [6] is zero.

  • Bit [5] gives the value of FPSCR[7]

  • Bits [4:0] give the value of FPSCR[4:0].


For additional information on the FPSCR, see the Cortex-A9 Floating-Point Unit (FPU) Technical Reference Manual and the Cortex-A9 NEON Media Processing Engine Technical Reference Manual.

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