Table A.29 shows the PTM interface signals. These signals are present only if the PTM interface is present.
In the I/O column, the I indicates an input from the PTM interface to the Cortex-A9 processor. The O indicates an output from the Cortex-A9 processor to the PTM. All these signals are in the Cortex-A9 clock domain.
|Name||I/O||Source or destination||Description|
Number of waypoints committed in this cycle. It is valid to indicate a valid waypoint and commit it in the same cycle.
Context ID for the waypoint.
This signal must be true regardless of the condition code of the waypoint.
If the processor Context ID has not been set, then WPTCONTEXTID[31:0] must report 0.
Waypoint flush signal.
The waypoint is a branch that updates the link register.
Only HIGH if WPTTYPE is a direct branch or an indirect branch.
Waypoint last executed address indicator.
This is the base Link Register in the case of an exception.
Equal to 0 if the waypoint is a reset exception.
Indicates the size of the last executed address when in Thumb state:
The waypoint passed its condition codes. The address is still used, irrespective of the value of this signal.
Must be set for all waypoints except branch.
J bit for waypoint destination.
Waypoint target address.
Bit  must be zero if the T bit is zero.
Bit  must be zero if the J bit is zero.
The value is zero if WPTTYPE is either prohibited or debug.
T bit for waypoint destination.
Trace is prohibited for the waypoint target.
Indicates entry to prohibited region. No more waypoints are traced until trace can resume.
This signal must be permanently asserted if NIDEN and DBGEN are both LOW, after the in-flight waypoints have exited the processor. Either an exception or a serial branch is required to ensure that changes to the inputs have been sampled.
Only one WPTVALID cycle must be seen with WPTTRACEPROHIBITED set.
Trace stops with this waypoint and the next waypoint is an Isync packet.
See the CoreSight PTM Architecture Specification for a description of the packets used in trace.
Debug Entry must be followed by Debug Exit.
Debug exit does not reflect the execution of an instruction.
Waypoint is confirmed as valid.
Instructions following the waypoint are executed in Non-secure state. An instruction is in Non-secure state if the NS bit is set and the processor is not in secure monitor mode.
See About system control for information about Security Extensions.
|O||There are no speculative waypoints in the PTM interface FIFO.|