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A.2. Reset signals

Table A.2 shows the reset and reset control signals.

Table A.2. Reset signals
NameI/OSourceDescription
nCPURESETIReset controllerCortex-A9 processor reset.
nDBGRESETICortex-A9 processor debug logic reset.
NEONCLKOFF[a]I

MPE SIMD logic clock control:

0

Do not cut MPE SIMD logic clock.

1

Cut MPE SIMD logic clock.

nNEONRESET[a]

I

Cortex-A9 MPE SIMD logic reset.

[a] Only if the MPE is present.


See Reset.

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