The ACTLR characteristics are:
parity checking, if implemented
allocation in one way
exclusive caching with the L2 cache
coherency mode, Symmetric Multiprocessing (SMP) or Asymmetric Multiprocessing (AMP)
speculative accesses on AXI
broadcast of cache, branch predictor, and TLB maintenance operations
write full line of zeros mode optimization for L2C-310 cache requests.
- Usage constraints
The ACTLR is:
Only accessible in privileged modes.
Common to the Secure and Non-secure states.
RW in Secure state.
RO in Non-secure state if NSACR.NS_SMP = 0.
RW in Non-secure state if NSACR.NS_SMP = 1. In this case all bits are Write Ignore except for the SMP bit.
Available in all configurations.
In all configurations when the SMP bit = 0, Inner Cacheable Shareable attributes are treated as Non-cacheable.
In multiprocessor configurations when the SMP bit is set:
broadcasting cache and TLB maintenance operations is permitted if the FW bit is set
receiving cache and TLB maintenance operations broadcast by other Cortex-A9 processors in the same coherent cluster is permitted if the FW bit is set
the Cortex-A9 processor can send and receive coherent requests for Shared Inner Write-back Write-Allocate accesses from other Cortex-A9 processors in the same coherent cluster.
See the register summary in Table 4.3.
Figure 4.9 shows the ACTLR bit assignments.
Table 4.36 shows the ACTLR bit assignments.
|[31:10]||-||UNP or SBZP.|
Support for parity checking, if implemented:
If parity checking is not implemented this bit reads as zero and writes are ignored.
|||Alloc in one way||Enable allocation in one cache way only. For use with memory copy operations to reduce cache pollution. The reset value is zero.|
Exclusive cache bit.
The exclusive cache configuration does not permit data to reside in L1 and L2 at the same time. The exclusive cache configuration provides support for only caching data on an eviction from L1 when the inner cache attributes are Write-Back, Cacheable and allocated in L1. Ensure that your cache controller is also configured for exclusive caching.
Signals if the Cortex-A9 processor is taking part in coherency or not.
In uniprocessor configurations, if this bit is set, then Inner Cacheable Shared is treated as Cacheable. The reset value is zero.
|||Write full line of zeros mode|
Enable write full line of zeros mode[a]. The reset value is zero.
|||L1 prefetch enable|
|||L2 prefetch enable|
Prefetch hint enable[a]. The reset value is zero.
Cache and TLB maintenance broadcast:
RAZ/WI if only one Cortex-A9 processor is present.
To access the ACTLR you must use a read modify write technique. To access the ACTLR, read or write the CP15 register with:
MRC p15, 0,<Rd>, c1, c0, 1; Read ACTLR MCR p15, 0,<Rd>, c1, c0, 1; Write ACTLR
Attempts to write to this register in secure privileged mode when CP15SDISABLE is HIGH result in an Undefined Instruction exception.