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4.3.6. Cache Level ID Register

The CLIDR characteristics are:

Purpose

Identifies:

  • the type of cache, or caches, implemented at each level

  • the Level of Coherency and Level of Unification for the cache hierarchy.

Usage constraints

The CLIDR is:

  • only accessible in privileged modes

  • common to the Secure and Non-secure states.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.6 shows the CLIDR bit assignments.

Figure 4.6. CLIDR bit assignments

Figure 4.6. CLIDR bit assignments

Table 4.33 shows the CLIDR bit assignments.

Table 4.33. CLIDR bit assignments
BitsNameFunction
[31:30]-UNP or SBZ
[29:27]LoU
b001

Level of unification.

[26:24]LoC
b001

Level of coherency.

[23:21]LoUIS
b001

Level of Unification Inner Shareable.

[20:18]CL 7
b000

no cache at CL 7

[17:15]CL 6
b000

no cache at CL 6

[14:12]CL 5
b000

no cache at CL 5

[11:9]CL 4
b000

no cache at CL 4

[8:6]CL 3
b000

no cache at CL 3

[5:3]CL 2
b000

no cache at CL 2

[2:0]CL 1
b011

separate instruction and data caches at CL 1


To access the CLIDR, read the CP15 register with:

MRC p15, 1,<Rd>, c0, c0, 1; Read CLIDR
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