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4.3.8. Cache Size Selection Register

The CSSELR characteristics are:


Selects the current CCSIDR. See the Cache Size Identification Register.

Usage constraints

The CSSELR is:

  • only accessible in privileged modes

  • banked for Secure and Non-secure states.


Available in all configurations.


See the register summary in Table 4.2.

Figure 4.7 shows the CSSELR bit assignments.

Figure 4.7. CSSELR bit assignments

Figure 4.7. CSSELR bit assignments

Table 4.34 shows the CSSELR bit assignments.

Table 4.34. CSSELR bit assignments
[31:4]-UNP or SBZ.

Cache level selected, RAZ/WI.

There is only one level of cache in the Cortex-A9 processor so the value for this field is b000.


Instruction not Data bit:


Data cache


Instruction cache.

To access the CSSELR, read the CP15 register with:

MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELRMCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR
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