The MIDR characteristics are:
Provides identification information for the processor, including an implementer code for the device and a device ID number.
- Usage constraints
The MIDR is:
a read-only register
common to the Secure and Non-secure states
only accessible in privileged modes.
Available in all configurations.
See the register summary in Table 4.2.
Figure 4.1 shows the MIDR bit assignments.
Table 4.28 shows the MIDR bit assignments.
Indicates the implementer code:
Indicates the variant number of the processor. This is the major revision number n in the rn part of the rnpn description of the product revision status, for example:
Indicates the architecture code:
|[15:4]||Primary part number|
Indicates the primary part number:
Indicates the minor revision number of the processor. This is the minor revision number n in the pn part of the rnpn description of the product revision status, for example:
To access the MIDR, read the CP15 register with:
MRC p15, 0, <Rt>, c0, c0, 0; Read Main ID Register