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4.3.18. PLE FIFO Status Register

The PLEFSR characteristics are:


Indicates how many entries remain available in the PLE FIFO.

Usage constraints

The PLEFSR is:

  • common to Secure and Non-secure states

  • accessible in User and privileged modes, regardless of any configuration bit.

NSAC.PLE controls Non-secure accesses.


Available in all Cortex-A9 configurations regardless of whether a PLE is present or not.


Figure 4.17 shows the PLEFSR bit assignments.

Figure 4.17. PLESFR bit assignments

Figure 4.17. PLESFR bit assignments

Table 4.44 shows the PLEFSR bit assignments.

Table 4.44. PLESFR bit assignments
[31:5]-Reserved, RAZ/WI.
[4:0]Available entries

Number of available entries in the PLE FIFO.

This is the difference between the total number of entries in the FIFO, that is configuration-specific, and the number of entries already programmed.

Use the PLESFR to check that an entry is available before programming a new PLE channel.

To access the PLESFR, read the CP15 register with:

MRC p15, 0, <Rt>, c11, c0, 4; Read the PLESFR
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