The Power Control Register characteristics are:
Enables you to set:
the clock latency for your implementation of the Cortex-A9 processor
dynamic clock gating.
- Usage constraints
a read/write register in Secure state
a read-only register in Non-secure state.
Available in all configurations.
See the register summary in Table 4.15.
Figure 4.21 shows the Power Control Register bit assignments.
Table 4.48 shows the Power Control Register bit assignments.
Samples the value present on the MAXCLKLATENCY pins on exit from reset.
This value reflects an implementation-specific parameter. ARM strongly recommends that the software does not modify it.
The max_clk_latency bits determine the length of the delay between when one of these blocks has its clock cut and the time when it can receive new active signals.
If the value determined by max_clk_latency is lower than the real delay, the block that had its clock cut can receive active signals even though it does not have a clock. This can cause the device to malfunction.
If the value determined by max_clk_latency is higher than the real delay, the master block waits extra cycles before sending its signals to the block that had its clock cut. This can have some performance impact.
When the value is correctly set, the block that had its clock cut receives active signals on the first clock edge of the wake-up. This gives optimum performance.
|||Enable dynamic clock gating||Disabled at reset.|
To access the Power Control Register, read or write the CP15 register with:
MRC p15,0,<Rd>,c15,c0,0; Read Power Control Register MCR p15,0,<Rd>,c15,c0,0; Write Power Control Register